| V1 |
|
83.33% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 2.000s | 23.499us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 42.554us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 77.527us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 11.000s | 916.881us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 2.000s | 101.193us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 2.000s | 239.574us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 77.527us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 101.193us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 3 | 3 | 100.00 | |||
| entropy_src_smoke | 2.000s | 23.499us | 1 | 1 | 100.00 | |
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 212.000s | 13022.554us | 1 | 1 | 100.00 | |
| firmware_mode | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov | 212.000s | 13022.554us | 1 | 1 | 100.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 368.000s | 13088.858us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| entropy_src_intr | 10.000s | 2162.034us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 5.000s | 2465.410us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 57.000s | 15472.970us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 31.873us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 3.000s | 82.663us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 85.004us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 1.000s | 389.692us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 2.000s | 40.732us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 2.000s | 40.732us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 42.554us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 77.527us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 101.193us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 105.959us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 42.554us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 77.527us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 101.193us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 105.959us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 2.000s | 155.687us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 2.000s | 185.812us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 128.657us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 212.000s | 13022.554us | 1 | 1 | 100.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 31.873us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 155.687us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 31.873us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 155.687us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 208.000s | 14039.643us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 31.873us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 155.687us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 31.873us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 155.687us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 31.873us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 5.000s | 2465.410us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 2.000s | 185.812us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 193.000s | 13062.523us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 7.000s | 1356.450us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_WARNING (uvm_reg_field.svh:1186) [RegModel] Trying to predict value of field 'observe_fifo_depth' while register 'entropy_src_reg_block.observe_fifo_depth' is being accessed | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 76994470362424387580836621749654416039374813514649381819905865220088694039027 | 268 |
UVM_FATAL @ 1356449681 ps: (entropy_src_scoreboard.sv:1601) [uvm_test_top.env.scoreboard] Check failed (ral.observe_fifo_depth.observe_fifo_depth.predict( ral.observe_fifo_depth.observe_fifo_depth.get_mirrored_value()-1, .kind(UVM_PREDICT_DIRECT)))
UVM_INFO @ 1356449681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails | 1 test run | |||
| entropy_src_csr_mem_rw_with_rand_reset | 67696496988889228381603756291365618469434426782377450095282826038457237439628 | 113 |
UVM_INFO @ 239574218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|