Simulation Results: flash_ctrl

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 94.25 %
  • assert
  • 96.94 %
  • func
  • 95.63 %
  • line
  • 95.97 %
  • branch
  • 97.12 %
  • cond
  • 93.91 %
  • toggle
  • 97.84 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 45.970s 62.698us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.820s 18.309us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.920s 382.799us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 54.970s 4305.560us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 23.520s 1539.539us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.600s 110.359us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
flash_ctrl_csr_aliasing 23.520s 1539.539us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.810s 17.336us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.310s 18.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.940s 48.727us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 13.110s 144.327us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1081.810s 167826.843us 1 1 100.00
flash_ctrl_hw_rma_reset 590.090s 110176.381us 1 1 100.00
flash_ctrl_lcmgr_intg 6.470s 23.386us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1007.530s 502043.844us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 238.120s 6995.192us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 83.390s 4229.802us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2406.840s 56355.021us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 47.550s 114.880us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.960s 91.486us 1 1 100.00
flash_ctrl_rw_evict_all_en 21.900s 86.658us 1 1 100.00
flash_ctrl_re_evict 23.070s 287.448us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 49.790s 46.827us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 49.790s 46.827us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 392.050s 21229.091us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.280s 226.482us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 376.980s 569.942us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 379.240s 11202.881us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 343.710s 882.123us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 870.460s 2137.599us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.930s 80.608us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 125.210s 5977.681us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.160s 17.564us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.710s 28.576us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 156.990s 142.429us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 18.270s 765.136us 1 1 100.00
flash_ctrl_otp_reset 45.180s 78.220us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1081.810s 167826.843us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 82.990s 453.918us 1 1 100.00
flash_ctrl_intr_wr 56.970s 11433.368us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 141.090s 9378.572us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 120.040s 23849.840us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 43.980s 2039.522us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 45.210s 1445.068us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.360s 57.389us 1 1 100.00
flash_ctrl_ro_derr 104.380s 1619.226us 1 1 100.00
flash_ctrl_rw_derr 122.380s 1761.789us 1 1 100.00
flash_ctrl_derr_detect 92.680s 616.242us 1 1 100.00
flash_ctrl_integrity 434.560s 18321.138us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.260s 106.674us 1 1 100.00
flash_ctrl_ro_serr 97.000s 908.277us 1 1 100.00
flash_ctrl_rw_serr 166.760s 4893.206us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 36.990s 5924.895us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 53.540s 1378.712us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 147.380s 24666.225us 1 1 100.00
flash_ctrl_write_word_sweep 8.440s 154.314us 1 1 100.00
flash_ctrl_read_word_sweep 7.690s 34.441us 1 1 100.00
flash_ctrl_ro 93.630s 2435.589us 1 1 100.00
flash_ctrl_rw 377.260s 18406.684us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.880s 838.463us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 623.040s 171485.345us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 37.910s 10035.724us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 7.510s 86.083us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.690s 32.512us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 12.850s 53.029us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 12.850s 53.029us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.920s 382.799us 1 1 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
flash_ctrl_csr_aliasing 23.520s 1539.539us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.620s 109.162us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.920s 382.799us 1 1 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
flash_ctrl_csr_aliasing 23.520s 1539.539us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.620s 109.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 31.010s 1529.717us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
flash_ctrl_tl_intg_err 426.130s 1371.258us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 426.130s 1371.258us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 426.130s 1371.258us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.940s 130.153us 1 1 100.00
flash_ctrl_wr_intg 6.780s 51.659us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 45.970s 62.698us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 45.180s 78.220us 1 1 100.00
flash_ctrl_disable 10.160s 17.564us 1 1 100.00
flash_ctrl_sec_info_access 44.930s 4855.132us 1 1 100.00
flash_ctrl_connect 7.710s 28.576us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.400s 45.728us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.780s 140.163us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.480s 27.400us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.160s 17.564us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.940s 130.153us 1 1 100.00
flash_ctrl_access_after_disable 6.010s 39.243us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.840s 28.638us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.160s 17.564us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.280s 226.482us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 377.260s 18406.684us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 166.760s 4893.206us 1 1 100.00
flash_ctrl_rw_derr 122.380s 1761.789us 1 1 100.00
flash_ctrl_integrity 434.560s 18321.138us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1081.810s 167826.843us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.890s 670.131us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.450s 22.172us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 10.640s 74.473us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1726.780s 3533.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 24.180s 56.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 344.700s 2797.679us 1 1 100.00