Simulation Results: hmac

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.76 %
  • code
  • 97.73 %
  • assert
  • 97.38 %
  • func
  • 44.18 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.920s 3785.184us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.820s 53.077us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.840s 37.086us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.480s 1178.251us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.290s 62.637us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.030s 15.313us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.840s 37.086us 1 1 100.00
hmac_csr_aliasing 2.290s 62.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 103.990s 48208.342us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 45.660s 6326.305us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 215.560s 19594.357us 1 1 100.00
hmac_test_sha384_vectors 19.960s 1170.067us 1 1 100.00
hmac_test_sha512_vectors 375.980s 60320.698us 1 1 100.00
hmac_test_hmac256_vectors 7.420s 1343.863us 1 1 100.00
hmac_test_hmac384_vectors 11.170s 1944.333us 1 1 100.00
hmac_test_hmac512_vectors 13.460s 907.813us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.160s 338.580us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 302.380s 3008.301us 1 1 100.00
error 1 1 100.00
hmac_error 26.150s 11885.376us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 22.830s 857.356us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.920s 3785.184us 1 1 100.00
hmac_long_msg 103.990s 48208.342us 1 1 100.00
hmac_back_pressure 45.660s 6326.305us 1 1 100.00
hmac_datapath_stress 302.380s 3008.301us 1 1 100.00
hmac_burst_wr 3.160s 338.580us 1 1 100.00
hmac_stress_all 921.050s 10250.204us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.920s 3785.184us 1 1 100.00
hmac_long_msg 103.990s 48208.342us 1 1 100.00
hmac_back_pressure 45.660s 6326.305us 1 1 100.00
hmac_datapath_stress 302.380s 3008.301us 1 1 100.00
hmac_wipe_secret 22.830s 857.356us 1 1 100.00
hmac_test_sha256_vectors 215.560s 19594.357us 1 1 100.00
hmac_test_sha384_vectors 19.960s 1170.067us 1 1 100.00
hmac_test_sha512_vectors 375.980s 60320.698us 1 1 100.00
hmac_test_hmac256_vectors 7.420s 1343.863us 1 1 100.00
hmac_test_hmac384_vectors 11.170s 1944.333us 1 1 100.00
hmac_test_hmac512_vectors 13.460s 907.813us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.920s 3785.184us 1 1 100.00
hmac_long_msg 103.990s 48208.342us 1 1 100.00
hmac_back_pressure 45.660s 6326.305us 1 1 100.00
hmac_datapath_stress 302.380s 3008.301us 1 1 100.00
hmac_burst_wr 3.160s 338.580us 1 1 100.00
hmac_error 26.150s 11885.376us 1 1 100.00
hmac_wipe_secret 22.830s 857.356us 1 1 100.00
hmac_test_sha256_vectors 215.560s 19594.357us 1 1 100.00
hmac_test_sha384_vectors 19.960s 1170.067us 1 1 100.00
hmac_test_sha512_vectors 375.980s 60320.698us 1 1 100.00
hmac_test_hmac256_vectors 7.420s 1343.863us 1 1 100.00
hmac_test_hmac384_vectors 11.170s 1944.333us 1 1 100.00
hmac_test_hmac512_vectors 13.460s 907.813us 1 1 100.00
hmac_stress_all 921.050s 10250.204us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 921.050s 10250.204us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.630s 28.971us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.640s 14.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.200s 410.604us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.200s 410.604us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.820s 53.077us 1 1 100.00
hmac_csr_rw 0.840s 37.086us 1 1 100.00
hmac_csr_aliasing 2.290s 62.637us 1 1 100.00
hmac_same_csr_outstanding 1.760s 43.637us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.820s 53.077us 1 1 100.00
hmac_csr_rw 0.840s 37.086us 1 1 100.00
hmac_csr_aliasing 2.290s 62.637us 1 1 100.00
hmac_same_csr_outstanding 1.760s 43.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.930s 302.298us 1 1 100.00
hmac_tl_intg_err 3.140s 3495.193us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.140s 3495.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.920s 3785.184us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.330s 159.689us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 16.350s 1339.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.060s 39.478us 1 1 100.00