Simulation Results

Simulation Results: i2c

11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.95 %

code
81.47 %

assert
97.25 %

func
82.14 %

line
96.38 %

branch
92.26 %

cond
85.23 %

toggle
89.45 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	36.650s	1565.618us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.220s	881.599us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.830s	28.661us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.790s	42.857us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.290s	90.523us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.630s	114.426us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.750s	18.166us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.790s	42.857us	1	1	100.00
	i2c_csr_aliasing	1.630s	114.426us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.850s	93.254us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3600.241s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	23.910s	7457.466us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.750s	21.407us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	33.820s	2808.587us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	71.540s	8180.046us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.970s	106.267us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.820s	2084.057us	1	1	100.00
	i2c_host_fifo_reset_rx	7.320s	947.459us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	49.040s	11347.130us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.430s	5391.737us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.670s	39.238us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.120s	2013.018us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	943.750s	49285.034us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.670s	840.901us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	20.620s	3102.503us	1	1	100.00
	i2c_target_intr_smoke	4.320s	4193.225us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.640s	274.360us	1	1	100.00
	i2c_target_fifo_reset_tx	1.640s	219.059us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	5.890s	10242.853us	1	1	100.00
	i2c_target_stress_rd	20.620s	3102.503us	1	1	100.00
	i2c_target_intr_stress_wr	19.170s	17605.850us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.590s	1345.721us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.460s	2624.967us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.210s	764.700us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.670s	616.150us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.320s	926.141us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.260s	313.858us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	23.910s	7457.466us	1	1	100.00
	i2c_host_perf_precise	10.920s	504.044us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.430s	5391.737us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.200s	105.134us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.780s	1110.073us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.870s	2139.532us	1	1	100.00
	i2c_target_nack_txstretch	1.170s	562.187us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	9.310s	414.149us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.760s	805.422us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.730s	32.502us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.840s	24.187us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.680s	196.360us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.680s	196.360us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.830s	28.661us	1	1	100.00
	i2c_csr_rw	0.790s	42.857us	1	1	100.00
	i2c_csr_aliasing	1.630s	114.426us	1	1	100.00
	i2c_same_csr_outstanding	1.060s	81.223us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.830s	28.661us	1	1	100.00
	i2c_csr_rw	0.790s	42.857us	1	1	100.00
	i2c_csr_aliasing	1.630s	114.426us	1	1	100.00
	i2c_same_csr_outstanding	1.060s	81.223us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.670s	120.050us	1	1	100.00
	i2c_sec_cm	1.150s	49.279us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.670s	120.050us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	13.310s	2203.417us	1
target_error_intr				1
	i2c_target_unexp_stop	0.840s	123.431us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	12.120s	1085.983us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	99703084854119277394253925906563159993002213896106087179892685544108786151686	88	UVM_INFO @ 2203417349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	22308437763640394706987774736232616928014870116284988069113812898974723159744	92	UVM_INFO @ 1085982719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	67178274312115922280822313819715488116979617694424021919351027032027266368660	88	UVM_INFO @ 93253682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_host_stress_all	39102793006263190847191373835003494277247982457421121336087699171213661294965	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	51408638513047716636907192165950723447231583610275840286884757796593720815220	84	UVM_INFO @ 2013017836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	60305149053927163406632406183660780585830826979820255494134923575450420390206	78	UVM_INFO @ 123430761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	104401604803220953706765344132404277271121380215729036350420878545219535279906	79	UVM_INFO @ 39238240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---