Simulation Results: keymgr

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.50 %
  • code
  • 94.36 %
  • assert
  • 97.72 %
  • func
  • 58.42 %
  • line
  • 98.68 %
  • branch
  • 97.81 %
  • cond
  • 93.84 %
  • toggle
  • 95.44 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.350s 274.852us 1 1 100.00
random 1 1 100.00
keymgr_random 2.970s 241.681us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.020s 70.365us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 6.250s 3305.337us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 2.720s 95.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.540s 35.593us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
keymgr_csr_aliasing 2.720s 95.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.630s 44.748us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 29.210s 1465.975us 1 1 100.00
keymgr_sideload_kmac 2.840s 75.030us 1 1 100.00
keymgr_sideload_aes 2.640s 207.642us 1 1 100.00
keymgr_sideload_otbn 13.540s 802.204us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.740s 33.496us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 4.360s 565.306us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.050s 54.280us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 5.210s 340.409us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.390s 102.329us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.990s 87.978us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 10.750s 832.400us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.870s 20.858us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.720s 31.457us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 3.520s 639.500us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 3.520s 639.500us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.020s 70.365us 1 1 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
keymgr_csr_aliasing 2.720s 95.338us 1 1 100.00
keymgr_same_csr_outstanding 1.550s 20.251us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.020s 70.365us 1 1 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
keymgr_csr_aliasing 2.720s 95.338us 1 1 100.00
keymgr_same_csr_outstanding 1.550s 20.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
keymgr_tl_intg_err 7.250s 516.153us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.280s 157.685us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.280s 157.685us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.280s 157.685us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.280s 157.685us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 7.150s 1268.476us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.250s 516.153us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.280s 157.685us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.630s 44.748us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.970s 241.681us 1 1 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.970s 241.681us 1 1 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.970s 241.681us 1 1 100.00
keymgr_csr_rw 0.810s 53.957us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 4.360s 565.306us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.390s 102.329us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.390s 102.329us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.970s 241.681us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.820s 297.717us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 6.240s 755.716us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 4.360s 565.306us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 6.240s 755.716us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 6.240s 755.716us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 6.240s 755.716us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.520s 8376.798us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 6.240s 755.716us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.540s 460.980us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 17322017770893172612850318978784427287845586020365375621535420901274413943531 148
UVM_INFO @ 460980375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---