Simulation Results: lc_ctrl/volatile_unlock_disabled

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.78 %
  • code
  • 84.07 %
  • assert
  • 94.69 %
  • func
  • 93.59 %
  • line
  • 97.19 %
  • branch
  • 93.70 %
  • cond
  • 79.15 %
  • toggle
  • 86.78 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.500s 255.662us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.160s 22.942us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.050s 33.363us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.730s 99.809us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 79.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.430s 31.913us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.050s 33.363us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 79.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.390s 52.747us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.880s 472.566us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 15.112us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.500s 348.094us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.740s 4812.453us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_prog_failure 1.500s 348.094us 1 1 100.00
lc_ctrl_errors 8.740s 4812.453us 1 1 100.00
lc_ctrl_security_escalation 6.570s 1184.118us 1 1 100.00
lc_ctrl_jtag_state_failure 48.060s 2273.112us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.160s 434.922us 1 1 100.00
lc_ctrl_jtag_errors 14.250s 3922.304us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.160s 889.490us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.660s 4818.037us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.160s 434.922us 1 1 100.00
lc_ctrl_jtag_errors 14.250s 3922.304us 1 1 100.00
lc_ctrl_jtag_access 11.150s 3209.886us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 21.190s 3707.797us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.010s 299.140us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.800s 64.264us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.980s 3390.765us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.730s 568.629us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.620s 70.634us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.060s 538.403us 1 1 100.00
lc_ctrl_jtag_alert_test 1.840s 61.306us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.650s 3370.765us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.120s 15.289us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 86.250s 31072.946us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 40.382us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.950s 54.812us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.950s 54.812us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 22.942us 1 1 100.00
lc_ctrl_csr_rw 1.050s 33.363us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 79.123us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.290s 51.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 22.942us 1 1 100.00
lc_ctrl_csr_rw 1.050s 33.363us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 79.123us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.290s 51.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 51.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 51.484us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.880s 472.566us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.980s 407.430us 1 1 100.00
lc_ctrl_sec_cm 6.180s 445.323us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.570s 1184.118us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.390s 52.747us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.660s 4818.037us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.290s 4589.294us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.290s 4589.294us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.420s 1940.094us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.240s 292.877us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.240s 292.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 13.200s 976.392us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 12276911235797468809091996102074113117353041323495389778962874483787336908934 1142
UVM_INFO @ 976392295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---