Simulation Results: lc_ctrl/volatile_unlock_enabled

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.53 %
  • code
  • 83.73 %
  • assert
  • 94.97 %
  • func
  • 92.88 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 78.58 %
  • toggle
  • 86.95 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.790s 63.552us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.750s 15.209us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 29.800us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.400s 43.640us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 411.890us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.860s 31.896us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 29.800us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 411.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.090s 223.580us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.640s 415.657us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.870s 36.194us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.760s 100.720us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.230s 407.480us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_prog_failure 1.760s 100.720us 1 1 100.00
lc_ctrl_errors 5.230s 407.480us 1 1 100.00
lc_ctrl_security_escalation 5.220s 1627.529us 1 1 100.00
lc_ctrl_jtag_state_failure 29.530s 3421.032us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.270s 259.242us 1 1 100.00
lc_ctrl_jtag_errors 23.240s 2190.595us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.890s 1141.909us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.430s 286.716us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.270s 259.242us 1 1 100.00
lc_ctrl_jtag_errors 23.240s 2190.595us 1 1 100.00
lc_ctrl_jtag_access 3.230s 342.970us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.320s 2199.105us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.460s 192.580us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.170s 110.457us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.910s 804.215us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.640s 1275.055us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.350s 167.833us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.980s 102.143us 1 1 100.00
lc_ctrl_jtag_alert_test 1.100s 156.241us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.980s 4796.385us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.220s 12.510us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 34.460s 18599.354us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 57.745us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.880s 53.775us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.880s 53.775us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 15.209us 1 1 100.00
lc_ctrl_csr_rw 0.820s 29.800us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 411.890us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 256.170us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 15.209us 1 1 100.00
lc_ctrl_csr_rw 0.820s 29.800us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 411.890us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 256.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 62.893us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 62.893us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.640s 415.657us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.450s 360.946us 1 1 100.00
lc_ctrl_sec_cm 6.640s 1008.754us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.220s 1627.529us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.090s 223.580us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.430s 286.716us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.620s 2445.696us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.620s 2445.696us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.680s 1033.311us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.930s 305.619us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.930s 305.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 14.630s 3529.870us 1 1 100.00