Simulation Results: otbn

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.63 %
  • code
  • 95.57 %
  • assert
  • 90.45 %
  • func
  • 97.88 %
  • block
  • 99.43 %
  • line
  • 99.56 %
  • branch
  • 92.73 %
  • toggle
  • 92.44 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 40.640us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 30.000s 43.334us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 28.000s 14.556us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 33.000s 90.933us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 30.000s 27.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 32.000s 128.142us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 28.000s 14.556us 1 1 100.00
otbn_csr_aliasing 30.000s 27.673us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 54.000s 12921.967us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 37.000s 4575.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 30.000s 470.218us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 50.000s 570.937us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 63.000s 209.783us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 78.000s 227.065us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 26.000s 97.898us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 10.962us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 94.779us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 31.000s 63.862us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 8.000s 33.255us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 77.982us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 77.982us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 30.000s 43.334us 1 1 100.00
otbn_csr_rw 28.000s 14.556us 1 1 100.00
otbn_csr_aliasing 30.000s 27.673us 1 1 100.00
otbn_same_csr_outstanding 3.000s 45.555us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 30.000s 43.334us 1 1 100.00
otbn_csr_rw 28.000s 14.556us 1 1 100.00
otbn_csr_aliasing 30.000s 27.673us 1 1 100.00
otbn_same_csr_outstanding 3.000s 45.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 15.000s 40.722us 1 1 100.00
otbn_dmem_err 31.000s 39.913us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 34.000s 97.095us 1 1 100.00
otbn_controller_ispr_rdata_err 32.000s 202.675us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 66.992us 1 1 100.00
otbn_urnd_err 4.000s 38.643us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 18.000s 11.175us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 101.529us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 32.795us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
otbn_tl_intg_err 20.000s 384.692us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 42.000s 485.472us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 40.640us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 31.000s 39.913us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 15.000s 40.722us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 20.000s 384.692us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 26.000s 97.898us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 15.000s 40.722us 1 1 100.00
otbn_dmem_err 31.000s 39.913us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 10.962us 0 1 0.00
otbn_illegal_mem_acc 18.000s 11.175us 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 15.000s 40.722us 1 1 100.00
otbn_dmem_err 31.000s 39.913us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 10.962us 0 1 0.00
otbn_illegal_mem_acc 18.000s 11.175us 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 26.000s 97.898us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 15.000s 40.722us 1 1 100.00
otbn_dmem_err 31.000s 39.913us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 10.962us 0 1 0.00
otbn_illegal_mem_acc 18.000s 11.175us 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 28.000s 68.783us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 38.997us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 45.000s 812.938us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 45.000s 812.938us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 33.461us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 223.055us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 102.853us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 102.853us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 60.544us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 63.000s 209.783us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 16.000s 375.234us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 55.125us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 242.000s 4953.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 89.000s 2014.909us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 31.380us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 88088389636323108120519157306620729686336983286762132884642991698291463487437 155
UVM_INFO @ 2014908606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 11313546728665642041975817239777733332342329810735931060614997785521028368268 105
UVM_ERROR @ 10962146 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10962146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---