Simulation Results: otp_ctrl

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.78 %
  • code
  • 79.23 %
  • assert
  • 94.05 %
  • func
  • 78.07 %
  • line
  • 88.54 %
  • branch
  • 83.36 %
  • cond
  • 90.02 %
  • toggle
  • 89.27 %
  • FSM
  • 44.97 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.540s 55.674us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.050s 247.850us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.360s 82.608us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.120s 296.937us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.830s 59.968us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.610s 128.169us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.360s 82.608us 1 1 100.00
otp_ctrl_csr_aliasing 2.830s 59.968us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.560s 568.094us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.690s 40.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.400s 827.306us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.110s 2689.595us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 13.490s 1654.199us 1 1 100.00
otp_ctrl_check_fail 15.780s 8125.805us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.640s 3386.964us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.380s 702.688us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.600s 677.355us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 17.860s 2637.415us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 15.720s 964.501us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 20.990s 1712.833us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 159.100s 116540.387us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.430s 76.307us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.290s 163.669us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.770s 1607.258us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.770s 1607.258us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.050s 247.850us 1 1 100.00
otp_ctrl_csr_rw 1.360s 82.608us 1 1 100.00
otp_ctrl_csr_aliasing 2.830s 59.968us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.600s 288.602us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.050s 247.850us 1 1 100.00
otp_ctrl_csr_rw 1.360s 82.608us 1 1 100.00
otp_ctrl_csr_aliasing 2.830s 59.968us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.600s 288.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
otp_ctrl_tl_intg_err 14.640s 2721.478us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.640s 2721.478us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_ctrl_macro_errs 15.720s 964.501us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_ctrl_macro_errs 15.720s 964.501us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.630s 235.273us 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.110s 2689.595us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 15.780s 8125.805us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 19.110s 12368.600us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.540s 25226.368us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.640s 3386.964us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.400s 1573.801us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 15.720s 964.501us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 12.210s 3974.190us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 31.910s 5450.048us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_macro_errs 115426619663646858699067432047543708672111637193539362522723957939118091995618 13054
UVM_INFO @ 964501159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112940740970861592437163391016420247173358930891528033378475023742521345124446 14300
UVM_INFO @ 5450047619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---