Simulation Results: pattgen

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.49 %
  • code
  • 98.87 %
  • assert
  • 98.17 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 49.085us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 49.277us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 26.345us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 612.152us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 31.376us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 58.937us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 26.345us 1 1 100.00
pattgen_csr_aliasing 1.000s 31.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 2587.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 2.000s 19.371us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 34.092us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 9.000s 123.498us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 56.572us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 53.288us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 382.833us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 382.833us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 49.277us 1 1 100.00
pattgen_csr_rw 2.000s 26.345us 1 1 100.00
pattgen_csr_aliasing 1.000s 31.376us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 18.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 49.277us 1 1 100.00
pattgen_csr_rw 2.000s 26.345us 1 1 100.00
pattgen_csr_aliasing 1.000s 31.376us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 18.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 96.258us 1 1 100.00
pattgen_sec_cm 1.000s 198.701us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 96.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
pattgen_stress_all_with_rand_reset 10.000s 1331.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 204.599us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pattgen_perf 76643870877491255688608920590311296011094553678960407919181273314729379230416 99
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---