Simulation Results: rom_ctrl/32kb

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.85 %
  • code
  • 98.16 %
  • assert
  • 97.53 %
  • func
  • 97.85 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.37 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.680s 184.881us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.790s 128.004us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.620s 2098.376us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.010s 293.379us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 542.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.820s 134.995us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.620s 2098.376us 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 542.490us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.020s 165.701us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.490s 123.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.440s 104.423us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.810s 1954.446us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.080s 715.530us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.650s 213.011us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.600s 169.547us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.600s 169.547us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.790s 128.004us 1 1 100.00
rom_ctrl_csr_rw 4.620s 2098.376us 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 542.490us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.800s 632.765us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.790s 128.004us 1 1 100.00
rom_ctrl_csr_rw 4.620s 2098.376us 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 542.490us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.800s 632.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.890s 1086.818us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 204.910s 977.993us 1 1 100.00
rom_ctrl_tl_intg_err 44.910s 980.756us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 204.910s 977.993us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 204.910s 977.993us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 204.910s 977.993us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 204.910s 977.993us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.680s 184.881us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.680s 184.881us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.680s 184.881us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 44.910s 980.756us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
rom_ctrl_kmac_err_chk 6.080s 715.530us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 63.950s 2426.774us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.890s 1086.818us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 204.910s 977.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 246.530s 6167.726us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 57879407916867040584250477254807508591264152568489371441002672054782094987174 79
UVM_INFO @ 104423297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---