Simulation Results: rom_ctrl/64kb

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.84 %
  • code
  • 99.26 %
  • assert
  • 97.24 %
  • func
  • 94.03 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 98.07 %
  • toggle
  • 99.97 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.790s 221.349us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.690s 215.119us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.470s 556.549us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.110s 214.022us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 287.580us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.160s 548.432us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.470s 556.549us 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 287.580us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.510s 1027.797us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.840s 296.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.770s 612.290us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.560s 803.957us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.350s 380.560us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.600s 4136.984us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.360s 287.566us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.360s 287.566us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.690s 215.119us 1 1 100.00
rom_ctrl_csr_rw 6.470s 556.549us 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 287.580us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.330s 529.796us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.690s 215.119us 1 1 100.00
rom_ctrl_csr_rw 6.470s 556.549us 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 287.580us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.330s 529.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 52.810s 45836.551us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 455.310s 2533.222us 1 1 100.00
rom_ctrl_tl_intg_err 52.490s 1285.033us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 455.310s 2533.222us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 455.310s 2533.222us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 455.310s 2533.222us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 455.310s 2533.222us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.790s 221.349us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.790s 221.349us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.790s 221.349us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.490s 1285.033us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
rom_ctrl_kmac_err_chk 12.350s 380.560us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 131.090s 34232.155us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 52.810s 45836.551us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 455.310s 2533.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 27.510s 10483.715us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 43457486555651856731002870207945311785034944682540878004680780359639212843298 79
UVM_INFO @ 612289865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---