Simulation Results: rstmgr

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.62 %
  • code
  • 99.41 %
  • assert
  • 98.93 %
  • func
  • 97.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.320s 259.743us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.930s 139.193us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.900s 90.448us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.250s 2472.891us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.380s 402.240us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.380s 176.690us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.900s 90.448us 1 1 100.00
rstmgr_csr_aliasing 2.380s 402.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.800s 172.657us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.270s 151.084us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.790s 74.789us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.740s 1633.049us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.740s 1633.049us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.740s 1633.049us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.740s 1633.049us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 31.650s 15455.605us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.990s 73.746us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.440s 241.952us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.440s 241.952us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 139.193us 1 1 100.00
rstmgr_csr_rw 0.900s 90.448us 1 1 100.00
rstmgr_csr_aliasing 2.380s 402.240us 1 1 100.00
rstmgr_same_csr_outstanding 1.130s 104.790us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 139.193us 1 1 100.00
rstmgr_csr_rw 0.900s 90.448us 1 1 100.00
rstmgr_csr_aliasing 2.380s 402.240us 1 1 100.00
rstmgr_same_csr_outstanding 1.130s 104.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 22.350s 16825.544us 1 1 100.00
rstmgr_tl_intg_err 1.520s 462.152us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 22.350s 16825.544us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 22.350s 16825.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.520s 462.152us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.030s 182.024us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.440s 1399.617us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.130s 302.405us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 22.350s 16825.544us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 90.448us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 90.448us 1 1 100.00