Simulation Results: rv_timer

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.41 %
  • code
  • 100.00 %
  • assert
  • 98.41 %
  • func
  • 93.82 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.620s 268.238us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 102.285us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.620s 24.491us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.280s 249.268us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 56.929us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.190s 23.621us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.620s 24.491us 1 1 100.00
rv_timer_csr_aliasing 0.730s 56.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.120s 7472.041us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.830s 2109.325us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.750s 414.388us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.750s 414.388us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.410s 4228.838us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 40.076us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 15.322us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.150s 28.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.150s 28.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 102.285us 1 1 100.00
rv_timer_csr_rw 0.620s 24.491us 1 1 100.00
rv_timer_csr_aliasing 0.730s 56.929us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 126.909us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 102.285us 1 1 100.00
rv_timer_csr_rw 0.620s 24.491us 1 1 100.00
rv_timer_csr_aliasing 0.730s 56.929us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 126.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 82.803us 1 1 100.00
rv_timer_tl_intg_err 0.790s 121.914us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.790s 121.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.590s 71.473us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.620s 180.515us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 42.620s 5721.357us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 96793676582140845700688149775459345469867958985947457133688833913652958091338 76
UVM_INFO @ 71472732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 53341784259710815405394741008112694067524341692139451195575811186441199206701 75
UVM_INFO @ 7472041143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 1900042064133823986927920622274878256523439337415724079983982249510355421837 75
UVM_INFO @ 180514613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---