Simulation Results: spi_device/2p

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.87 %
  • code
  • 93.87 %
  • assert
  • 95.38 %
  • func
  • 62.35 %
  • line
  • 98.91 %
  • branch
  • 98.25 %
  • cond
  • 95.24 %
  • toggle
  • 87.57 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 25.830s 3221.598us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.160s 47.101us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.670s 292.845us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 10.460s 1137.967us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.640s 2664.141us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.720s 74.032us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.670s 292.845us 1 1 100.00
spi_device_csr_aliasing 10.640s 2664.141us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.790s 35.474us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.180s 77.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.750s 19.111us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.900s 122.253us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.790s 60.802us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.970s 972.245us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.970s 972.245us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.180s 621.164us 1 1 100.00
spi_device_tpm_sts_read 0.830s 77.808us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 3.470s 1690.487us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.130s 821.041us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.570s 959.321us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.570s 959.321us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.240s 4406.161us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.240s 4406.161us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.240s 4406.161us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.240s 4406.161us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.240s 4406.161us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.570s 3904.710us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 13.280s 14566.376us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 13.280s 14566.376us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 13.280s 14566.376us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.640s 310.696us 1 1 100.00
spi_device_read_buffer_direct 3.550s 202.645us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 13.280s 14566.376us 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 28.110s 2439.583us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.850s 247.636us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.850s 247.636us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 14.630s 1918.232us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 25.830s 3221.598us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 285.220s 105441.253us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 135.200s 88314.215us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.770s 12.701us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.780s 68.656us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.630s 129.960us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.630s 129.960us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.160s 47.101us 1 1 100.00
spi_device_csr_rw 1.670s 292.845us 1 1 100.00
spi_device_csr_aliasing 10.640s 2664.141us 1 1 100.00
spi_device_same_csr_outstanding 1.990s 90.469us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.160s 47.101us 1 1 100.00
spi_device_csr_rw 1.670s 292.845us 1 1 100.00
spi_device_csr_aliasing 10.640s 2664.141us 1 1 100.00
spi_device_same_csr_outstanding 1.990s 90.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.020s 447.579us 1 1 100.00
spi_device_tl_intg_err 10.990s 716.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.990s 716.159us 1 1 100.00