Simulation Results: spi_host

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.21 %
  • code
  • 95.03 %
  • assert
  • 96.79 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 16.000s 8322.933us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 53.599us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 106.764us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 46.433us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 46.426us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 42.939us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 106.764us 1 1 100.00
spi_host_csr_aliasing 1.000s 46.426us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.425us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 24.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 65.001us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 717.355us 1 1 100.00
spi_host_error_cmd 1.000s 19.503us 1 1 100.00
spi_host_event 12.000s 609.732us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 210.991us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 210.991us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 210.991us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 134.000s 14511.977us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 202.396us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 221.257us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 210.991us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 210.991us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 16.000s 8322.933us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 16.000s 8322.933us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 7.000s 581.138us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 961.226us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 27.000s 10519.190us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 679.937us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 717.355us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 34.104us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 35.400us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 83.550us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 83.550us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 53.599us 1 1 100.00
spi_host_csr_rw 1.000s 106.764us 1 1 100.00
spi_host_csr_aliasing 1.000s 46.426us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 22.984us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 53.599us 1 1 100.00
spi_host_csr_rw 1.000s 106.764us 1 1 100.00
spi_host_csr_aliasing 1.000s 46.426us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 22.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 61.371us 1 1 100.00
spi_host_sec_cm 1.000s 134.847us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 61.371us 1 1 100.00