Simulation Results: sram_ctrl/main

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 96.77 %
  • assert
  • 98.10 %
  • func
  • 94.00 %
  • block
  • 96.10 %
  • line
  • 96.83 %
  • branch
  • 94.17 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 2934.853us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 29.990us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.701us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 210.433us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.748us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1330.298us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.701us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.748us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 185.000s 5908.162us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 98.000s 4871.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 41.000s 58614.631us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 80.000s 2737.064us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 120.000s 4275.405us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 4318.110us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 34.000s 11501.853us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 778.030us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2958.714us 1 1 100.00
sram_ctrl_partial_access_b2b 251.000s 29439.236us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 672.336us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 685.745us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 899.004us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 6133.136us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1344.914us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 324.000s 570495.756us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 24.570us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 56.834us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 56.834us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 29.990us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.701us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.748us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.420us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 29.990us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.701us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 49.748us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 46137.959us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 496.009us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 615.860us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 496.009us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 615.860us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 6133.136us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 6133.136us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.701us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 778.030us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 778.030us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 778.030us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 34.000s 11501.853us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 2672.634us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 46137.959us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 736.966us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2934.853us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2934.853us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 778.030us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 496.009us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 34.000s 11501.853us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 496.009us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 496.009us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 2934.853us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 496.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 28.000s 1701.896us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 48179649672914637933147591568170340489675008996072430191654539987118977617478 86
UVM_INFO @ 672336026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 46792972789622000346471698532537431389602746369012887954330843920535947955397 86
UVM_INFO @ 685745455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 99142277693210210393574847041232961244181635648127547640424711556239591556026 86
UVM_INFO @ 899004114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---