Simulation Results: sysrst_ctrl

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.58 %
  • code
  • 93.61 %
  • assert
  • 95.50 %
  • func
  • 61.62 %
  • line
  • 97.71 %
  • branch
  • 97.70 %
  • cond
  • 95.30 %
  • toggle
  • 99.77 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 5.410s 2109.805us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.370s 2469.470us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.630s 2258.965us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.430s 2522.321us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 5.430s 6017.018us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.230s 2083.357us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 36.370s 38992.119us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.880s 2635.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.370s 2086.056us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.230s 2083.357us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.880s 2635.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 34.940s 53273.718us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 44.190s 24579.182us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.630s 4062.180us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.960s 3040.237us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.960s 2524.562us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.170s 2178.224us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.130s 3794.504us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.990s 2627.664us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.710s 9932.007us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 69.290s 38048.131us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.250s 7120.864us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.090s 2079.192us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.250s 2020.054us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.360s 3883.197us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.360s 3883.197us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.430s 6017.018us 1 1 100.00
sysrst_ctrl_csr_rw 2.230s 2083.357us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.880s 2635.478us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 1.870s 4811.120us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.430s 6017.018us 1 1 100.00
sysrst_ctrl_csr_rw 2.230s 2083.357us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.880s 2635.478us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 1.870s 4811.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 38.670s 22015.099us 1 1 100.00
sysrst_ctrl_tl_intg_err 17.010s 43173.263us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 17.010s 43173.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.600s 5761.830us 1 1 100.00