Simulation Results: uart

 
11/06/2026 15:30:28 DVSim: v1.49.9 sha: 69b7df1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.49 %
  • code
  • 94.63 %
  • assert
  • 98.27 %
  • func
  • 42.58 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 91.83 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.320s 493.175us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 26.869us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.700s 49.356us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.530s 90.885us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.750s 40.977us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.970s 62.626us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.700s 49.356us 1 1 100.00
uart_csr_aliasing 0.750s 40.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 17.060s 71760.764us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.320s 493.175us 1 1 100.00
uart_tx_rx 17.060s 71760.764us 1 1 100.00
parity_error 2 2 100.00
uart_intr 6.230s 9507.647us 1 1 100.00
uart_rx_parity_err 16.850s 183772.715us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 17.060s 71760.764us 1 1 100.00
uart_intr 6.230s 9507.647us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 38.690s 89838.554us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 80.960s 64336.284us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 7.080s 21160.811us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 6.230s 9507.647us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 6.230s 9507.647us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 6.230s 9507.647us 1 1 100.00
perf 1 1 100.00
uart_perf 88.460s 8120.192us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 26.780s 7766.388us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 26.780s 7766.388us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.120s 11567.457us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.840s 4361.861us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.530s 1341.585us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 26.200s 6492.855us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 64.120s 50773.732us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 59.980s 34294.594us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.560s 12.328us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.630s 14.909us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.000s 172.355us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.000s 172.355us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 26.869us 1 1 100.00
uart_csr_rw 0.700s 49.356us 1 1 100.00
uart_csr_aliasing 0.750s 40.977us 1 1 100.00
uart_same_csr_outstanding 0.960s 19.480us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 26.869us 1 1 100.00
uart_csr_rw 0.700s 49.356us 1 1 100.00
uart_csr_aliasing 0.750s 40.977us 1 1 100.00
uart_same_csr_outstanding 0.960s 19.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.900s 80.555us 1 1 100.00
uart_tl_intg_err 1.350s 70.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.350s 70.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 11.650s 9861.589us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 2 test runs
uart_noise_filter 75241646916808495496982399927713496146471119675825957357586274459199643458754 78
UVM_ERROR @ 11233679365 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11233679365 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 11279679319 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 6, rx_q.size = 0
UVM_ERROR @ 11281345984 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 5, rx_q.size = 0
uart_stress_all_with_rand_reset 49730617513438107934224238985316313672289883844137875332498201740679461288947 110
UVM_ERROR @ 8512129184 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8523898403 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 8523898403 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8535744545 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all 2956066025871440174572083707560401122477804031818247752533583784799757009015 82
UVM_ERROR @ 32760107325 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 32761232361 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 32768107581 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 32879923659 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr