Simulation Results: adc_ctrl

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.40 %
  • code
  • 91.06 %
  • assert
  • 92.06 %
  • func
  • 13.09 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 85.90 %
  • toggle
  • 99.53 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 7.540s 5823.696us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.010s 1230.301us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.370s 486.520us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 6.270s 27272.191us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.420s 942.344us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.970s 570.226us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.370s 486.520us 1 1 100.00
adc_ctrl_csr_aliasing 2.420s 942.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.000s 287.844us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.210s 367.016us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.910s 455.240us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.710s 346.786us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.140s 468.184us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.700s 460.531us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.680s 397.254us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.820s 464.958us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.530s 3379.137us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 45.860s 41682.042us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 106.990s 141887.241us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.750s 771.074us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.180s 330.684us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.720s 373.882us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.720s 417.058us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.720s 417.058us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.010s 1230.301us 1 1 100.00
adc_ctrl_csr_rw 1.370s 486.520us 1 1 100.00
adc_ctrl_csr_aliasing 2.420s 942.344us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.600s 2343.911us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.010s 1230.301us 1 1 100.00
adc_ctrl_csr_rw 1.370s 486.520us 1 1 100.00
adc_ctrl_csr_aliasing 2.420s 942.344us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.600s 2343.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 0.980s 4505.785us 1 1 100.00
adc_ctrl_tl_intg_err 7.370s 4601.946us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 7.370s 4601.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.690s 1666.423us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 103692153058342936470124010080735566682928169610927379506510734690215706440112 386
UVM_INFO @ 287844288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 109763727277583361843644255537012694494440801340324354624152454813078711597715 386
UVM_INFO @ 367015622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 111347101386650810970086395265522044412458466286887193362035327272563169539293 386
UVM_INFO @ 455239500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 20764673586953370838344082584948080251956508968664435166104023199332464244570 386
UVM_INFO @ 346786264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 11199476212495697921429937904640829257212692009755386053553201825387430899201 386
UVM_INFO @ 468183832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 86135648530349334084784178161649166988751984652536557355383578257002216732925 386
UVM_INFO @ 460530861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 112139772788838974216318210319079494017226144250238881099869884084047866837745 386
UVM_INFO @ 464957697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 89477767788205359616598811282450428456923260933765890889779476344696676073577 386
UVM_INFO @ 397253790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 101668804290152766298419668660132795692889593733211905496125163642935179754951 422
UVM_INFO @ 1666422786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 84598344701759875678090434440059569637904095728513474232847879419319629155565 387
UVM_INFO @ 771073665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---