Simulation Results: aes/masked

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.39 %
  • code
  • 94.66 %
  • assert
  • 98.38 %
  • func
  • 75.14 %
  • block
  • 95.07 %
  • line
  • 95.92 %
  • branch
  • 89.16 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 364.799us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 126.708us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 58.950us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 93.023us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1274.543us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 194.692us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 73.483us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 93.023us 1 1 100.00
aes_csr_aliasing 2.000s 194.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 126.708us 1 1 100.00
aes_config_error 2.000s 133.490us 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 126.708us 1 1 100.00
aes_config_error 2.000s 133.490us 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 154.818us 1 1 100.00
aes_b2b 5.000s 117.841us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 126.708us 1 1 100.00
aes_config_error 2.000s 133.490us 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
aes_alert_reset 3.000s 369.883us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 102.456us 1 1 100.00
aes_config_error 2.000s 133.490us 1 1 100.00
aes_alert_reset 3.000s 369.883us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 137.125us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 777.281us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 369.883us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 154.818us 1 1 100.00
aes_sideload 3.000s 241.808us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 123.879us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 13.000s 319.669us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 84.870us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 207.745us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 207.745us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.950us 1 1 100.00
aes_csr_rw 1.000s 93.023us 1 1 100.00
aes_csr_aliasing 2.000s 194.692us 1 1 100.00
aes_same_csr_outstanding 2.000s 80.129us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.950us 1 1 100.00
aes_csr_rw 1.000s 93.023us 1 1 100.00
aes_csr_aliasing 2.000s 194.692us 1 1 100.00
aes_same_csr_outstanding 2.000s 80.129us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 65.158us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 73.804us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 431.750us 1 1 100.00
aes_tl_intg_err 1.000s 264.104us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 264.104us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 369.883us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 126.708us 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
aes_alert_reset 3.000s 369.883us 1 1 100.00
aes_core_fi 3.000s 370.077us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 133.490us 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
aes_core_fi 3.000s 370.077us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.730us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 83.755us 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 154.818us 1 1 100.00
aes_sideload 3.000s 241.808us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 83.755us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 83.755us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 83.755us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 83.755us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 83.755us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 154.818us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 144.573us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
aes_ctr_fi 2.000s 55.428us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 144.573us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 144.573us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_ctr_fi 2.000s 55.428us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 144.573us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
aes_ctr_fi 2.000s 55.428us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 369.883us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
aes_ctr_fi 2.000s 55.428us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
aes_ctr_fi 2.000s 55.428us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_ctr_fi 2.000s 55.428us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 144.573us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 144.573us 0 1 0.00
aes_control_fi 2.000s 53.564us 1 1 100.00
aes_cipher_fi 3.000s 68.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 7.138us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 58055165970741688561477888323334845506598403280250212255470776288873217817605 9532
UVM_INFO @ 65158106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 107369480863642553854340653076188667646903766163344942189370931742448853101242 6550
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 15645515370243896775556148810125618557672597611237008311168922678880271852771 155
UVM_INFO @ 7137999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---