Simulation Results: aes/unmasked

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.48 %
  • code
  • 90.13 %
  • assert
  • 97.92 %
  • func
  • 74.38 %
  • block
  • 90.40 %
  • line
  • 91.93 %
  • branch
  • 81.71 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 64.851us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 92.239us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 192.875us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 68.403us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 705.903us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 312.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 147.956us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 68.403us 1 1 100.00
aes_csr_aliasing 2.000s 312.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 92.239us 1 1 100.00
aes_config_error 2.000s 94.995us 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 92.239us 1 1 100.00
aes_config_error 2.000s 94.995us 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 556.157us 1 1 100.00
aes_b2b 5.000s 662.271us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 92.239us 1 1 100.00
aes_config_error 2.000s 94.995us 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
aes_alert_reset 2.000s 136.179us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 57.887us 1 1 100.00
aes_config_error 2.000s 94.995us 1 1 100.00
aes_alert_reset 2.000s 136.179us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 144.281us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 369.011us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 136.179us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 556.157us 1 1 100.00
aes_sideload 2.000s 97.243us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 828.385us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 20.000s 1522.416us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 66.267us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 271.423us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 271.423us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 192.875us 1 1 100.00
aes_csr_rw 2.000s 68.403us 1 1 100.00
aes_csr_aliasing 2.000s 312.363us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.782us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 192.875us 1 1 100.00
aes_csr_rw 2.000s 68.403us 1 1 100.00
aes_csr_aliasing 2.000s 312.363us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 105.357us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 216.926us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 720.827us 1 1 100.00
aes_tl_intg_err 2.000s 186.395us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 186.395us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 136.179us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 92.239us 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
aes_alert_reset 2.000s 136.179us 1 1 100.00
aes_core_fi 2.000s 88.774us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 94.995us 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
aes_core_fi 2.000s 88.774us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 155.740us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 64.431us 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 556.157us 1 1 100.00
aes_sideload 2.000s 97.243us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 64.431us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 64.431us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 64.431us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 64.431us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 64.431us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 556.157us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 153.700us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
aes_ctr_fi 1.000s 50.251us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 153.700us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 153.700us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_ctr_fi 1.000s 50.251us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 153.700us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
aes_ctr_fi 1.000s 50.251us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 136.179us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
aes_ctr_fi 1.000s 50.251us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
aes_ctr_fi 1.000s 50.251us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_ctr_fi 1.000s 50.251us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 153.700us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 153.700us 0 1 0.00
aes_control_fi 2.000s 56.663us 1 1 100.00
aes_cipher_fi 1.000s 45.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 10.545us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 38674421570814023763129717473356182034729777976939733741380957295671304237812 5734
UVM_INFO @ 105356780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 70265972939518279877038863012028937796382332088189782799629188236650593896514 7295
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:1082) virtual_sequencer [aes_stress_vseq] 1 test run
aes_stress_all_with_rand_reset 60775539353164086457740977760149638440094703336029510154365028850871393741968 160
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0