Simulation Results

Simulation Results: chip

15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
75.18 %

code
84.88 %

assert
97.37 %

func
43.28 %

line
94.33 %

branch
93.84 %

cond
90.51 %

toggle
88.60 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		76.26%
V2S		100.00%
V3		65.38%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	166.400s	3322.717us	1	1	100.00
	chip_sw_example_rom	88.290s	2871.018us	1	1	100.00
	chip_sw_example_manufacturer	140.320s	3117.617us	1	1	100.00
	chip_sw_example_concurrency	157.440s	2645.054us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	300.310s	7412.373us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	403.050s	5312.974us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	267.330s	5267.540us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4655.320s	37648.412us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	318.620s	6150.307us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4655.320s	37648.412us	1	1	100.00
	chip_csr_rw	403.050s	5312.974us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.920s	46.607us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	295.640s	4816.331us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	295.640s	4816.331us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	295.640s	4816.331us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	369.140s	4616.110us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	369.140s	4616.110us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	341.580s	4370.018us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	346.710s	4796.562us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	402.130s	4409.555us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	946.850s	8032.300us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1004.240s	8409.054us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	245.240s	4572.335us	1	1	100.00

212/278 passed

76.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	138.010s	4941.553us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	138.010s	4941.553us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	209.870s	3820.200us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	277.850s	5415.992us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	259.680s	5394.685us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	237.880s	4497.630us	1	1	100.00
	chip_tap_straps_testunlock0	437.330s	7721.154us	1	1	100.00
	chip_tap_straps_rma	233.630s	4569.376us	1	1	100.00
	chip_tap_straps_prod	119.910s	3136.510us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	173.740s	3182.556us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	784.760s	9587.420us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	495.220s	5475.567us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	495.220s	5475.567us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	637.400s	8962.956us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	720.850s	9344.300us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	412.270s	4295.320us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	615.640s	6092.195us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3803.470s	19490.680us	1	1	100.00
	chip_sw_aes_enc_jitter_en	182.050s	2846.582us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	642.380s	6804.688us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	128.730s	2342.852us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1125.910s	9446.969us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	206.860s	3043.791us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	426.820s	5573.118us	1	1	100.00
	chip_sw_clkmgr_jitter	188.830s	3755.751us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	236.770s	3673.557us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	286.660s	4020.054us	0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	307.180s	5548.432us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	127.100s	2518.624us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	307.180s	5548.432us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	145.630s	2978.736us	1	1	100.00
	chip_sw_aes_smoketest	193.440s	3101.097us	1	1	100.00
	chip_sw_aon_timer_smoketest	217.200s	3712.795us	1	1	100.00
	chip_sw_clkmgr_smoketest	154.800s	2770.441us	1	1	100.00
	chip_sw_csrng_smoketest	141.600s	2431.905us	1	1	100.00
	chip_sw_entropy_src_smoketest	917.940s	6999.607us	1	1	100.00
	chip_sw_gpio_smoketest	172.420s	3272.700us	1	1	100.00
	chip_sw_hmac_smoketest	195.780s	2956.103us	1	1	100.00
	chip_sw_kmac_smoketest	187.440s	2899.953us	1	1	100.00
	chip_sw_otbn_smoketest	1701.350s	11256.046us	1	1	100.00
	chip_sw_pwrmgr_smoketest	297.350s	6507.067us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	257.460s	5867.926us	1	1	100.00
	chip_sw_rv_plic_smoketest	141.240s	3497.395us	1	1	100.00
	chip_sw_rv_timer_smoketest	174.540s	2747.639us	1	1	100.00
	chip_sw_rstmgr_smoketest	189.730s	3249.749us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	193.350s	3608.000us	1	1	100.00
	chip_sw_uart_smoketest	158.090s	2453.128us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	195.990s	2672.148us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	399.700s	5699.211us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8211.130s	62604.738us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	2966.640s	15367.590us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	33.503s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	235.410s	4008.100us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	217.140s	3699.660us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7539.220s	55408.023us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7587.150s	57971.239us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	168.990s	3272.324us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	168.990s	3272.324us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4655.320s	37648.412us	1	1	100.00
	chip_same_csr_outstanding	1560.330s	17206.647us	1	1	100.00
	chip_csr_hw_reset	300.310s	7412.373us	1	1	100.00
	chip_csr_rw	403.050s	5312.974us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4655.320s	37648.412us	1	1	100.00
	chip_same_csr_outstanding	1560.330s	17206.647us	1	1	100.00
	chip_csr_hw_reset	300.310s	7412.373us	1	1	100.00
	chip_csr_rw	403.050s	5312.974us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	31.510s	536.731us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.230s	42.604us	1	1	100.00
	xbar_smoke_large_delays	52.890s	9470.996us	1	1	100.00
	xbar_smoke_slow_rsp	53.460s	5555.730us	1	1	100.00
	xbar_random_zero_delays	31.840s	570.870us	1	1	100.00
	xbar_random_large_delays	35.110s	5947.322us	1	1	100.00
	xbar_random_slow_rsp	268.980s	30274.080us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	27.830s	976.094us	1	1	100.00
	xbar_error_and_unmapped_addr	26.760s	1144.638us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	36.170s	1639.498us	1	1	100.00
	xbar_error_and_unmapped_addr	26.760s	1144.638us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	6.610s	170.605us	1	1	100.00
	xbar_access_same_device_slow_rsp	262.110s	32695.429us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	34.750s	1599.370us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	453.300s	19542.939us	1	1	100.00
	xbar_stress_all_with_error	276.100s	11162.783us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	116.380s	2691.583us	1	1	100.00
	xbar_stress_all_with_reset_error	87.530s	349.480us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	2966.640s	15367.590us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2650.510s	34009.886us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	2986.980s	14802.615us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	117.272s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	8.518s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	9.588s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	34.140s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	13.549s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	61.674s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.144s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	20.094s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	37.576s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	61.671s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	135.277s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	51.819s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	29.100s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.493s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	43.935s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.880s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	19.010s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.980s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.620s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	20.880s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.770s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.670s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	23.490s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.930s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.300s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.900s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.480s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.010s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.470s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	21.710s	10.380us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	138.174s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	70.928s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	64.003s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	70.358s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	68.441s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5895.380s	31085.745us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6069.500s	28505.740us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	3314.680s	16567.638us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3048.030s	16196.794us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2829.730s	35160.666us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2829.730s	35160.666us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	156.920s	2679.518us	1	1	100.00
	chip_sw_aes_enc_jitter_en	182.050s	2846.582us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	165.230s	3057.846us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	191.170s	3580.981us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1525.100s	11380.998us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	183.060s	3358.151us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	392.680s	5405.345us	1	1	100.00
chip_sw_all_escalation_resets				0	1	0.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	561.950s	5262.013us	1	1	100.00
	chip_plic_all_irqs_10	302.970s	4267.022us	1	1	100.00
	chip_plic_all_irqs_20	464.240s	4742.888us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	162.220s	3151.244us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1286.860s	12162.189us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	335.330s	5469.826us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	158.590s	3567.152us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.163s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	959.020s	7309.086us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	831.860s	7250.931us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	810.470s	8009.601us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7655.110s	254846.875us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	250.970s	4117.022us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	297.350s	6507.067us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	250.970s	4117.022us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	508.900s	8636.851us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	508.900s	8636.851us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	366.390s	6890.695us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	374.170s	4913.944us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	601.750s	6509.207us	1	1	100.00
	chip_sw_aes_idle	191.170s	3580.981us	1	1	100.00
	chip_sw_hmac_enc_idle	205.710s	2665.509us	1	1	100.00
	chip_sw_kmac_idle	134.880s	3085.107us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	231.950s	4580.142us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	225.460s	4010.080us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	351.920s	4394.597us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	367.830s	5349.370us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	855.370s	11906.087us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	383.150s	4511.051us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	391.050s	4919.310us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	370.530s	3847.465us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	372.500s	4682.853us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	414.060s	4253.707us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	390.810s	4734.674us	1	1	100.00
	chip_sw_ast_clk_outputs	637.400s	8962.956us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	299.510s	6856.221us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	370.530s	3847.465us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	372.500s	4682.853us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	412.270s	4295.320us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	615.640s	6092.195us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3803.470s	19490.680us	1	1	100.00
	chip_sw_aes_enc_jitter_en	182.050s	2846.582us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	642.380s	6804.688us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	128.730s	2342.852us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1125.910s	9446.969us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	206.860s	3043.791us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	426.820s	5573.118us	1	1	100.00
	chip_sw_clkmgr_jitter	188.830s	3755.751us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	113.780s	2406.499us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	419.460s	4762.441us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	663.470s	7701.387us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3980.980s	24763.790us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	167.170s	3583.520us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	216.350s	3353.522us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1164.800s	10882.329us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	190.500s	3455.647us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	349.260s	4927.283us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1040.050s	19026.440us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	4387.900s	31842.735us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	637.400s	8962.956us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	398.910s	5144.637us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	300.550s	3931.625us	1	1	100.00
chip_sw_clkmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	959.020s	7309.086us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2232.450s	24211.803us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	344.540s	4796.875us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	558.450s	8440.476us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	160.070s	3133.298us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3241.550s	17515.040us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	187.180s	3333.674us	1	1	100.00
	chip_sw_edn_entropy_reqs	722.950s	6524.110us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	187.180s	3333.674us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2232.450s	24211.803us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	169.020s	2824.746us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1475.420s	24962.871us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	635.160s	5252.859us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	615.640s	6092.195us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	377.010s	3731.333us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	412.270s	4295.320us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3418.950s	44306.656us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1475.420s	24962.871us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	200.310s	3876.432us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1620.330s	12201.512us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	143.440s	2817.278us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3418.950s	44306.656us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	143.440s	2817.278us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	143.440s	2817.278us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	143.440s	2817.278us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	143.440s	2817.278us	0	1	0.00
chip_sw_flash_lc_escalate_en				0	1	0.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	248.930s	7932.903us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	521.470s	5398.601us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	428.390s	6027.608us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	428.390s	6027.608us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	138.310s	2929.327us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	128.730s	2342.852us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	205.710s	2665.509us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1637.180s	12026.821us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1663.780s	12018.586us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	446.410s	4819.572us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	389.660s	5077.926us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	398.510s	5613.263us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	274.560s	3912.729us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1620.330s	12201.512us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1125.910s	9446.969us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	709.430s	7621.438us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1525.100s	11380.998us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4454.150s	20018.308us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	129.680s	2535.327us	1	1	100.00
	chip_sw_kmac_mode_kmac	191.050s	3607.309us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	206.860s	3043.791us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1620.330s	12201.512us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	149.390s	3232.791us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1222.080s	9566.456us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	134.880s	3085.107us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	392.680s	5405.345us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	237.880s	4497.630us	1	1	100.00
	chip_tap_straps_rma	233.630s	4569.376us	1	1	100.00
	chip_tap_straps_prod	119.910s	3136.510us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	188.840s	2811.071us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1237.820s	9906.957us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	143.440s	2817.278us	0	1	0.00
	chip_sw_flash_rma_unlocked	3418.950s	44306.656us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	213.360s	3743.086us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	567.740s	7916.623us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	578.890s	6917.142us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	461.890s	5295.783us	0	1	0.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
	chip_sw_keymgr_key_derivation	1620.330s	12201.512us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	294.980s	9023.141us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	544.180s	10438.979us	1	1	100.00
	chip_prim_tl_access	248.930s	7932.903us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	299.510s	6856.221us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	383.150s	4511.051us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	391.050s	4919.310us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	370.530s	3847.465us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	372.500s	4682.853us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	414.060s	4253.707us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	390.810s	4734.674us	1	1	100.00
	chip_tap_straps_dev	237.880s	4497.630us	1	1	100.00
	chip_tap_straps_rma	233.630s	4569.376us	1	1	100.00
	chip_tap_straps_prod	119.910s	3136.510us	1	1	100.00
	chip_rv_dm_lc_disabled	155.650s	5695.253us	0	1	0.00
chip_lc_scrap				3	4	75.00
	chip_sw_lc_ctrl_rma_to_scrap	136.810s	3249.486us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	71.870s	2499.906us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	83.270s	3624.289us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	1939.680s	26763.620us	0	1	0.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1892.090s	36617.233us	1	1	100.00
	chip_rv_dm_lc_disabled	155.650s	5695.253us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	862.230s	26003.763us	0	1	0.00
	chip_sw_lc_walkthrough_prod	594.290s	9640.199us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	641.790s	10034.367us	1	1	100.00
	chip_sw_lc_walkthrough_rma	422.800s	5885.755us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1892.090s	36617.233us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	78.470s	2815.122us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	56.230s	2039.398us	1	1	100.00
	rom_volatile_raw_unlock	32.016s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3831.060s	17972.809us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3803.470s	19490.680us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	601.750s	6509.207us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	601.750s	6509.207us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	601.750s	6509.207us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	290.810s	3841.659us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1475.420s	24962.871us	1	1	100.00
	chip_sw_otbn_mem_scramble	290.810s	3841.659us	1	1	100.00
	chip_sw_keymgr_key_derivation	1620.330s	12201.512us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	294.720s	4549.458us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.850s	2420.033us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1475.420s	24962.871us	1	1	100.00
	chip_sw_otbn_mem_scramble	290.810s	3841.659us	1	1	100.00
	chip_sw_keymgr_key_derivation	1620.330s	12201.512us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	294.720s	4549.458us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.850s	2420.033us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	305.280s	4839.662us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	188.840s	2811.071us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	213.360s	3743.086us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	567.740s	7916.623us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	578.890s	6917.142us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	461.890s	5295.783us	0	1	0.00
	chip_sw_lc_ctrl_transition	330.110s	6678.888us	1	1	100.00
	chip_prim_tl_access	248.930s	7932.903us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	248.930s	7932.903us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	892.050s	7950.288us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	141.720s	5819.141us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	932.270s	25103.288us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	255.770s	7603.412us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	318.750s	7837.182us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	369.900s	6302.413us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1050.510s	22056.402us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1074.500s	14962.866us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	508.900s	8636.851us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	432.520s	7348.954us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	290.460s	5024.784us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	141.720s	5819.141us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	245.010s	4283.699us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	596.800s	11959.959us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	412.930s	7877.224us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	191.800s	3499.568us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1521.410s	22109.942us	1	1	100.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	712.780s	7190.984us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1242.580s	12724.477us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1578.040s	27621.340us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	209.030s	3941.236us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	294.980s	9023.141us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	294.980s	9023.141us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				4	4	100.00
	chip_sw_pwrmgr_all_reset_reqs	1242.580s	12724.477us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1521.410s	22109.942us	1	1	100.00
	chip_sw_pwrmgr_wdog_reset	290.460s	5024.784us	1	1	100.00
	chip_sw_pwrmgr_smoketest	297.350s	6507.067us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	265.200s	4438.931us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	375.260s	5313.144us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	265.940s	5285.722us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1286.860s	12162.189us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	149.750s	2995.714us	1	1	100.00
chip_sw_rstmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	831.860s	7250.931us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	504.800s	4802.911us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	470.510s	4611.055us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	203.200s	3402.480us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.850s	2420.033us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	375.260s	5313.144us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	375.260s	5313.144us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	674.110s	10533.426us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	840.850s	14069.857us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	265.200s	4438.931us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	154.720s	3441.447us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	349.170s	6059.352us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	233.630s	4569.376us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	155.650s	5695.253us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	561.950s	5262.013us	1	1	100.00
	chip_plic_all_irqs_10	302.970s	4267.022us	1	1	100.00
	chip_plic_all_irqs_20	464.240s	4742.888us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	198.410s	2902.072us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	202.180s	3384.837us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	2966.640s	15367.590us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	372.390s	5747.689us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	219.100s	3487.522us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	192.360s	3816.697us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	145.620s	2524.669us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	294.720s	4549.458us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	426.820s	5573.118us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	400.450s	7164.732us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	500.000s	8613.135us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	544.180s	10438.979us	1	1	100.00
chip_sw_sram_lc_escalation				1	2	50.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
	chip_sw_data_integrity_escalation	495.220s	5475.567us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	712.780s	7190.984us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1117.850s	23374.998us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	164.490s	3188.017us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	206.650s	3484.253us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	322.570s	4437.874us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1117.850s	23374.998us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1117.850s	23374.998us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2502.670s	21101.861us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2502.670s	21101.861us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	276.590s	5662.916us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2829.730s	35160.666us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	158.550s	3297.983us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	148.450s	2799.310us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	311.240s	3531.109us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	348.700s	4509.035us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	953.120s	8410.537us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5300.940s	31469.151us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1868.240s	12540.136us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	141.670s	2887.559us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	211.890s	3601.222us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	90.130s	2709.774us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10210.170s	72239.317us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1160.550s	6990.745us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	205.440s	3962.796us	0	1	0.00
	rom_e2e_jtag_debug_dev	426.600s	5828.302us	0	1	0.00
	rom_e2e_jtag_debug_rma	159.660s	4740.264us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	67.520s	2889.231us	0	1	0.00
	rom_e2e_jtag_inject_dev	296.300s	5273.099us	1	1	100.00
	rom_e2e_jtag_inject_rma	50.560s	2393.292us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	50.143s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	254.780s	4010.579us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	347.130s	3177.325us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	479.320s	3692.616us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1512.870s	11123.745us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	224.800s	2229.878us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	608.120s	5448.603us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	140.240s	2784.941us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	183.880s	3608.056us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	277.500s	5829.225us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	365.180s	5873.212us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1242.580s	12724.477us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	205.440s	3962.796us	0	1	0.00
	rom_e2e_jtag_debug_dev	426.600s	5828.302us	0	1	0.00
	rom_e2e_jtag_debug_rma	159.660s	4740.264us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	475.670s	6407.561us	1	1	100.00
chip_sw_plic_alerts				0	1	0.00
	chip_sw_all_escalation_resets	165.060s	2853.397us	0	1	0.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5511.890s	38063.939us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5511.890s	38063.939us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	173.340s	3815.120us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	369.140s	4616.110us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3075.760s	19090.313us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	190.790s	2887.948us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	21.220s	10.400us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.000s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	164.850s	3331.018us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	159.920s	2973.148us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	278.280s	4139.238us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	9.059s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	237.170s	3241.544us	1	1	100.00
	ate_bootstrap_flash_erase	591.370s	10010.400us	0	1	0.00
	ate_bootstrap_one_frame	6628.650s	45331.040us	1	1	100.00
	ate_bootstrap_disjoint	9701.040s	84811.879us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	69454567444429035952700990230560333019824158541250495161865020714730902215435	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29483389143481799782770890027224532927236046487430571576537735503829162206522	None	Another command (pid=439970) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=478280) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=516358) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	36197192804827801258438316410248783364733716224518574383227590262090865015541	None	---- STDERR ---- Another command (pid=574890) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	50854483032149904577789180581799318088038422417980002826259939983830647176435	None	Another command (pid=574890) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=576468) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=593063) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	71992640641560077489923398345287489336195868125986738182060925631508313073517	None	Another command (pid=648401) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=617064) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=650965) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	65911555545139997191396276114016111020731223580527660902868991728890100025776	None	Another command (pid=591558) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=606247) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=606672) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	6428150207415030489581045323611563710314516428209093628739447960643920675342	None	Another command (pid=470072) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=471873) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=475653) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	79223006749217870118467196518430119135282846960232497432772851141975170650335	None	Another command (pid=588798) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=574890) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=503999) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	10591123306347194939996587736037529365947502950118116423292203199373686121718	None	Another command (pid=591558) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=606247) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=606672) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	47623890138008234597523478237309290097579017462685957747295645487820790879779	None	Another command (pid=647278) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=623502) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=617064) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	81920380360769223290797482466507624375335059918540031086345597447668259509051	None	Another command (pid=635508) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=665281) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=699487) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	51479181551737652022418434120901817381093812212630429667801011027716553875836	None	Another command (pid=578548) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=580176) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=495575) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	70422940113870180232091783724423578600249833261333114933798774420946373509573	None	Another command (pid=377617) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=575490) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=578548) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	105616176714696483600974907229653109413128194953932951244296551894565144096304	None	---- STDERR ---- Another command (pid=423478) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=477789) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16501723041373268881995493272066164056334490731333366190902417049937014379573	None	Another command (pid=495719) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=494825) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=423478) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	23461420091144376032773162074423099803315895817296657544249952598722195757965	None	Another command (pid=639913) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=661073) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=594966) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	42247065137671148461167330517064753848815123433252392606098412916137147731566	None	Another command (pid=439970) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=478280) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=516358) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	60240099254875669557479232136119187376408955041909063149573123166012463442945	None	Another command (pid=578548) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=572312) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=580176) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	68801711787599346993895227904461186520302138663602099610776940584725446341971	None	Another command (pid=516358) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=443051) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=479815) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	70003134378230784536236314721574794666950357458754239350507797275238927151622	None	Another command (pid=577627) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=578548) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=580176) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	71636568741587944910455115245948527342932735879315262709896427774898119094787	None	Another command (pid=570735) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=588798) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=574890) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	38097726642740882863544465527712899733049482094160954696184690622421851355575	None	Another command (pid=470072) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=471873) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=475653) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	12254832217303732231045053872289119540213097264843354564752395937902093992155	None	Another command (pid=470072) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=471873) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=475653) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	61349141585202132491766280280978323645065475943608160610172874593229391472235	None	Another command (pid=379652) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=470072) is running. Waiting for it to complete on the server (server_pid=273122)... Another command (pid=427184) is running. Waiting for it to complete on the server (server_pid=273122)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	62123033203779824976395214178242139682269851947702013126640036901828191723278	366	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	92749755485104501700174947864327195334432568699740641941253139384181714642373	368	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	3919237826786750954662943333473784541214424423923212307745824005661428440994	365	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	2629948844241096872982850485748245770430574173401829071227162017412300847652	328	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	64182969974342481001897223296261009938178144145661079792647835185659285514217	327	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3216139798562501627029948944625484902421453897116050726088766679364130970227	328	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	104555732494882949298502391372721224977405994572615823351968485002417174603424	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	50281837552761816615412571025072960409906734211280070390093785736323565194306	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	42658100156188843510669525160888141042211523234986100017635718794795516608376	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	43617136621265726128420240775034796718895952210445330672763198440370771346791	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	2267347780284594362261322646880741386564536539241119443054239266820072556069	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	88158559227811043712641156512032503405901971741465185490529914851486682564790	310	UVM_INFO @ 12026.821055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	107983933540891400278593649076675653031658593864498445845352404133536374333657	310	UVM_INFO @ 12018.586074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	43856889582909186301335604240847596888997313465253233982121677784262176559125	336	UVM_INFO @ 20018.308386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	63551699319885979256647832155951722025211830242650269378220489008462630308664	325	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	48431026482153013109547727511383617456202562437671610272047958899872094961408	326	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	37735811206215936640201978308983074903890132065653539165726284207381042048351	326	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				2 test runs
	chip_sw_lc_walkthrough_prod	104677275789924960865093921095043557819525503114296571322104366136000381937120	369	UVM_INFO @ 9640.199493 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	10195112759031495183913859370705834810114363253971432380352286664955075619851	341	UVM_INFO @ 5885.755058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				2 test runs
	chip_sw_pwrmgr_deep_sleep_por_reset	112254072747802076243024874295162817426994750734025894482861221034351419553506	325	UVM_ERROR @ 7837.182000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7837.182000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	81673796888949496589753107568875722020045640136286487187846420274072287901561	319	UVM_ERROR @ 8636.851000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8636.851000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	18125713095751663056768242638033355642101948570768277941328530256707963744032	313	UVM_ERROR @ 3499.568396 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3499.568396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13578358395460946456430065529307215862137565772642144006599568401865384533096	340	UVM_ERROR @ 11959.959055 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 11959.959055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	96119825952410282783804883193434128192559234938009987334284044229116973508869	363	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	14001406750120261193213385645562023701403613034559809753240958588458785352339	325	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	91133362723832816079651183673674741041154744564916335568104502203220814264674	364	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	101278657119034902280480512276439785557420818706454571100851669951462261930084	328	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected , got				1 test run
	chip_sw_all_escalation_resets	77315141932773364705761684888167409027955893758002496239992026378001187070969	317	UVM_INFO @ 2853.396548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	77669722405096194866360545902937004868225430146250976288581635349298376401745	301	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	28760604474594809106083087432565797972799925054310773633020232307344822213831	327	UVM_INFO @ 3487.522010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	32631486030873038804151949233729173080185246030755423763376018229078104886186	309	UVM_INFO @ 2817.277774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	544249585510440802743042543574837009795162764049966098857569204665376314681	342	UVM_INFO @ 5295.782652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	103460150662851032557362576353698903139887732815863207132490014931035307513094	316	UVM_ERROR @ 3608.056440 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3608.056440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	273382854345606029436870010594889763697871606940762405602679344866712749986	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_rand_to_scrap	85529807614962667190272163217596700198940308019051604320946766240828787094144	313	UVM_INFO @ 26763.619951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_dev	27360044430044134351264031721075792060356662853881876662516941891384661366370	308	UVM_INFO @ 26003.762895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	63571891342570334607893470441968057288576489051273124852002648299881285347772	318	UVM_ERROR @ 5819.140577 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 5819.140577 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	84534235336914550329236929468031793098737730482946539945737013892831734491657	341	UVM_ERROR @ 7348.953684 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 7348.953684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49629092720600914464773447375047050724851078893144523248816649618942954859517	332	UVM_INFO @ 35160.666048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	10985954216766370648335944190466831026517654970875110833275380651965242838797	307	UVM_INFO @ 3358.151236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	114128071851249555192039552141317933150293332837312642614310306701166501825200	308	UVM_INFO @ 3567.151962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	23519889895128439035051724125951905725913156282430253667179848373852366753412	None
Offending '(reset_cause == HwReq)'				1 test run
	chip_sw_sensor_ctrl_alert	23517655926089779942970072158519032815252867705180491981933629556387684240380	331	UVM_ERROR @ 4020.054056 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A UVM_INFO @ 4020.054056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	25757011033376331136928584465873011012778639580321180082257014711950789615989	343	UVM_INFO @ 4010.578507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	80714202397708558123694416662144716310400357637980478278207032026401703217261	246	UVM_INFO @ 5695.253330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	3724970205913558523212894678284545327985209418484520873666404497389610927242	312	UVM_INFO @ 4008.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	12211424911310185113855136504022411248449192475311310322985989526119943174162	319	UVM_INFO @ 3699.660000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	85658132448881765927939338345348967110674235598914767563542964355357804000970	327	UVM_INFO @ 9344.299797 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	86838039467459480600247336006220831837596242377356128704117833757758443964696	272	UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	59840360643819275866686931517455095055703925462661065035445660118674867519750	325	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	82977675607529019020294384742435796611771260603093214333958524044158146718515	327	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds				1 test run
	rom_e2e_jtag_debug_test_unlocked0	21011107522959586048629518844419629279109403376496989543669724490663497918806	318	UVM_INFO @ 3962.795759 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_invalid_meas	101724127704705188824640387557503964504304161174967393607684584511805006280462	319	UVM_INFO @ 16567.638475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	33226364861846602771402191791933901419971104249944308943450377525858824424970	327	UVM_ERROR @ 5699.210864 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 5699.210864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---