Simulation Results: clkmgr

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.21 %
  • code
  • 97.66 %
  • assert
  • 94.07 %
  • func
  • 84.91 %
  • line
  • 98.81 %
  • branch
  • 98.43 %
  • cond
  • 91.87 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.910s 24.523us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.140s 181.595us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.780s 149.423us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.270s 173.023us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.380s 32.965us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
clkmgr_csr_aliasing 1.270s 173.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 41.653us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.870s 76.954us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.060s 33.550us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.900s 20.376us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.910s 24.523us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.930s 1292.447us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.070s 153.500us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.930s 1292.447us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 18.950s 5826.380us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.990s 73.825us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.580s 110.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.580s 110.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.140s 181.595us 1 1 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
clkmgr_csr_aliasing 1.270s 173.023us 1 1 100.00
clkmgr_same_csr_outstanding 1.060s 37.275us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.140s 181.595us 1 1 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
clkmgr_csr_aliasing 1.270s 173.023us 1 1 100.00
clkmgr_same_csr_outstanding 1.060s 37.275us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.860s 15.407us 0 1 0.00
clkmgr_tl_intg_err 37.170s 10041.397us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 793.570s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 793.570s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 793.570s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 793.570s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.080s 139.830us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 37.170s 10041.397us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.930s 1292.447us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.070s 153.500us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 793.570s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.840s 30.230us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.930s 100.525us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.670s 18.656us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.980s 45.311us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.090s 42.671us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.860s 15.407us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.880s 62.021us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.860s 15.407us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.760s 431.671us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 16.850s 1717.033us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 62450083380469176031359075275370832212021221555474059622168867843460128461552 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 68296665305083083835746559799724173216780056807616840231419223749655537460716 85
UVM_INFO @ 15406667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 114047547970387644401781812898964531395010406363449353157048615942078617018397 161
UVM_INFO @ 10041396590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---