Simulation Results: csrng

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.25 %
  • code
  • 91.66 %
  • assert
  • 94.10 %
  • func
  • 69.99 %
  • block
  • 96.25 %
  • line
  • 96.98 %
  • branch
  • 90.83 %
  • toggle
  • 93.10 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 54.216us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 44.716us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 16.926us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 36.000s 2667.357us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 33.421us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 18.010us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 16.926us 1 1 100.00
csrng_csr_aliasing 2.000s 33.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
alerts 1 1 100.00
csrng_alert 12.000s 707.157us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 6.000s 347.058us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 6.000s 347.058us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 108.000s 2810.806us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 16.550us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 20.481us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 88.971us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 88.971us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 44.716us 1 1 100.00
csrng_csr_rw 2.000s 16.926us 1 1 100.00
csrng_csr_aliasing 2.000s 33.421us 1 1 100.00
csrng_same_csr_outstanding 3.000s 105.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 44.716us 1 1 100.00
csrng_csr_rw 2.000s 16.926us 1 1 100.00
csrng_csr_aliasing 2.000s 33.421us 1 1 100.00
csrng_same_csr_outstanding 3.000s 105.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
csrng_tl_intg_err 4.000s 242.999us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 2.565us 0 1 0.00
csrng_csr_rw 2.000s 16.926us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 12.000s 707.157us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 108.000s 2810.806us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 12.000s 707.157us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 108.000s 2810.806us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 12.000s 707.157us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 242.999us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
csrng_sec_cm 2.000s 47.434us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 138.098us 1 1 100.00
csrng_err 2.000s 25.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 135.000s 6437.689us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 99368207367231828291265023834331488635093374101723451862545469730239121623123 100
UVM_INFO @ 347057658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 85945714062257534237623289133968322759387756170933554698656804743406149351699 99
UVM_INFO @ 2564631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---