Simulation Results: edn/edn0

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.96 %
  • code
  • 78.49 %
  • assert
  • 95.01 %
  • func
  • 78.37 %
  • line
  • 96.74 %
  • branch
  • 88.28 %
  • cond
  • 82.59 %
  • toggle
  • 78.08 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 17.881us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.050s 20.329us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.870s 77.609us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.280s 1242.822us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.380s 61.433us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.410s 94.455us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.870s 77.609us 1 1 100.00
edn_csr_aliasing 1.380s 61.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.190s 64.725us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.190s 64.725us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.190s 64.725us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 68.644us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.180s 56.722us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 27.464us 1 1 100.00
disable 1 2 50.00
edn_disable 0.860s 11.940us 1 1 100.00
edn_disable_auto_req_mode 0.830s 15.788us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 5.190s 429.257us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.880s 15.879us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.030s 62.125us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.460s 23.830us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.460s 23.830us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.050s 20.329us 1 1 100.00
edn_csr_rw 0.870s 77.609us 1 1 100.00
edn_csr_aliasing 1.380s 61.433us 1 1 100.00
edn_same_csr_outstanding 1.040s 26.465us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.050s 20.329us 1 1 100.00
edn_csr_rw 0.870s 77.609us 1 1 100.00
edn_csr_aliasing 1.380s 61.433us 1 1 100.00
edn_same_csr_outstanding 1.040s 26.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.560s 640.766us 1 1 100.00
edn_tl_intg_err 1.710s 298.667us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 32.402us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.180s 56.722us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.560s 640.766us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.560s 640.766us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.560s 640.766us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.560s 640.766us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.180s 56.722us 1 1 100.00
edn_sec_cm 7.560s 640.766us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.180s 56.722us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.710s 298.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 66.700s 11430.952us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 99918682547619471228853911788965785753807522323798434807135065633969558626787 149
UVM_INFO @ 11430952414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 45873858908208863739132223836506502785881282811060141277132280186229188843681 88
UVM_INFO @ 15788317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---