Simulation Results: edn/edn1

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.84 %
  • code
  • 82.21 %
  • assert
  • 98.70 %
  • func
  • 79.62 %
  • line
  • 98.10 %
  • branch
  • 93.72 %
  • cond
  • 89.38 %
  • toggle
  • 87.80 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 38.975us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 14.739us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.880s 13.876us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.680s 169.381us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.940s 48.499us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.440s 101.400us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.880s 13.876us 1 1 100.00
edn_csr_aliasing 0.940s 48.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.020s 35.737us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.020s 35.737us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.020s 35.737us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 36.864us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.160s 92.679us 1 1 100.00
errs 1 1 100.00
edn_err 0.860s 40.660us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 18.539us 1 1 100.00
edn_disable_auto_req_mode 1.020s 55.843us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.260s 286.870us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 30.331us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.880s 12.011us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.420s 108.031us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.420s 108.031us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 14.739us 1 1 100.00
edn_csr_rw 0.880s 13.876us 1 1 100.00
edn_csr_aliasing 0.940s 48.499us 1 1 100.00
edn_same_csr_outstanding 1.060s 119.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 14.739us 1 1 100.00
edn_csr_rw 0.880s 13.876us 1 1 100.00
edn_csr_aliasing 0.940s 48.499us 1 1 100.00
edn_same_csr_outstanding 1.060s 119.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.200s 592.771us 1 1 100.00
edn_tl_intg_err 1.840s 338.592us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 25.437us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.160s 92.679us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.200s 592.771us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.200s 592.771us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.200s 592.771us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.200s 592.771us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.160s 92.679us 1 1 100.00
edn_sec_cm 2.200s 592.771us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.160s 92.679us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.840s 338.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 57.440s 10394.206us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 105768362434944659269573315675165710273902499590643894304654811121235603712393 228
UVM_INFO @ 10394205537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---