Simulation Results: entropy_src/rng_4bits

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.60 %
  • code
  • 88.19 %
  • assert
  • 85.06 %
  • func
  • 53.55 %
  • block
  • 94.56 %
  • line
  • 97.19 %
  • branch
  • 86.86 %
  • toggle
  • 75.99 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 101.278us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 24.987us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 49.333us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 468.977us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 57.128us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 11.455us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 49.333us 1 1 100.00
entropy_src_csr_aliasing 2.000s 57.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 101.278us 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
entropy_src_fw_ov 144.000s 14078.329us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 144.000s 14078.329us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 163.000s 14225.599us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
entropy_src_intr 9.000s 2705.489us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
entropy_src_functional_alerts 4.000s 179.240us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 55.000s 14139.491us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 218.095us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 92.606us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 25.821us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 37.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 159.180us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 159.180us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 24.987us 1 1 100.00
entropy_src_csr_rw 1.000s 49.333us 1 1 100.00
entropy_src_csr_aliasing 2.000s 57.128us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 148.166us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 24.987us 1 1 100.00
entropy_src_csr_rw 1.000s 49.333us 1 1 100.00
entropy_src_csr_aliasing 2.000s 57.128us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 148.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 226.102us 1 1 100.00
entropy_src_tl_intg_err 3.000s 99.053us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
entropy_src_cfg_regwen 1.000s 25.629us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
entropy_src_fw_ov 144.000s 14078.329us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 218.095us 1 1 100.00
entropy_src_sec_cm 2.000s 226.102us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 218.095us 1 1 100.00
entropy_src_sec_cm 2.000s 226.102us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 122.000s 14052.733us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 218.095us 1 1 100.00
entropy_src_sec_cm 2.000s 226.102us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 218.095us 1 1 100.00
entropy_src_sec_cm 2.000s 226.102us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 218.095us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 179.240us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 99.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 210.000s 14112.368us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 2.000s 90.456us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 97906260837602248639487078608202278878555060078102635612442367393593271114640 120
UVM_INFO @ 90455631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 104994972595729652663257654615667690221743281253709171859716565904758737049646 113
UVM_INFO @ 11454561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---