Simulation Results: flash_ctrl

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.58 %
  • code
  • 94.10 %
  • assert
  • 96.85 %
  • func
  • 95.79 %
  • line
  • 95.96 %
  • branch
  • 97.19 %
  • cond
  • 93.74 %
  • toggle
  • 97.89 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 74.940s 156.014us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.080s 60.496us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.510s 247.290us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 51.150s 4144.059us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 21.990s 775.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.860s 324.771us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
flash_ctrl_csr_aliasing 21.990s 775.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.280s 151.724us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.920s 19.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.870s 97.741us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 12.500s 58.105us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1229.200s 161077.717us 1 1 100.00
flash_ctrl_hw_rma_reset 527.990s 70147.062us 1 1 100.00
flash_ctrl_lcmgr_intg 7.920s 209.920us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 957.290s 973153.027us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 131.120s 785.440us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.490s 24.188us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 3067.480s 677282.173us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 41.780s 102.367us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.390s 38.517us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.910s 38.845us 1 1 100.00
flash_ctrl_re_evict 15.560s 131.505us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 164.930s 2830.559us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 164.930s 2830.559us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 335.720s 19840.376us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.460s 698.934us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 144.360s 163.511us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 379.480s 48131.014us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 296.880s 4163.018us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1149.160s 1093.330us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.870s 23.802us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 139.800s 6325.188us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.270s 34.804us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.640s 83.787us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 88.370s 113.348us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 50.950s 1255.503us 1 1 100.00
flash_ctrl_otp_reset 63.400s 695.473us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1229.200s 161077.717us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 128.280s 9366.987us 1 1 100.00
flash_ctrl_intr_wr 52.850s 24459.280us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 240.090s 177631.669us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 132.260s 30908.587us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 37.340s 2135.330us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 38.990s 684.018us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.490s 106.267us 1 1 100.00
flash_ctrl_ro_derr 119.080s 1031.975us 1 1 100.00
flash_ctrl_rw_derr 118.820s 1499.571us 1 1 100.00
flash_ctrl_derr_detect 108.930s 3466.526us 1 1 100.00
flash_ctrl_integrity 346.830s 4786.104us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 13.430s 91.664us 1 1 100.00
flash_ctrl_ro_serr 102.200s 4401.417us 1 1 100.00
flash_ctrl_rw_serr 101.050s 1306.527us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 45.620s 6256.941us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 65.360s 4485.800us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 117.230s 6587.277us 1 1 100.00
flash_ctrl_write_word_sweep 6.980s 44.581us 1 1 100.00
flash_ctrl_read_word_sweep 8.280s 72.661us 1 1 100.00
flash_ctrl_ro 87.880s 757.594us 1 1 100.00
flash_ctrl_rw 410.000s 4812.761us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.190s 537.385us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 595.080s 151561.026us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 107.700s 10028.499us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.950s 156.738us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.420s 75.165us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 13.000s 199.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 13.000s 199.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.510s 247.290us 1 1 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
flash_ctrl_csr_aliasing 21.990s 775.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.910s 1215.831us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.510s 247.290us 1 1 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
flash_ctrl_csr_aliasing 21.990s 775.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.910s 1215.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 51.700s 1509.339us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
flash_ctrl_tl_intg_err 412.600s 1259.094us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 412.600s 1259.094us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 412.600s 1259.094us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.040s 74.651us 1 1 100.00
flash_ctrl_wr_intg 7.440s 51.011us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 74.940s 156.014us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 63.400s 695.473us 1 1 100.00
flash_ctrl_disable 9.270s 34.804us 1 1 100.00
flash_ctrl_sec_info_access 44.390s 836.202us 1 1 100.00
flash_ctrl_connect 8.640s 83.787us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.690s 79.051us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.470s 258.100us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 26.200s 47.072us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.270s 34.804us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.040s 74.651us 1 1 100.00
flash_ctrl_access_after_disable 6.090s 70.393us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.090s 70.753us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.270s 34.804us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.460s 698.934us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 410.000s 4812.761us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 101.050s 1306.527us 1 1 100.00
flash_ctrl_rw_derr 118.820s 1499.571us 1 1 100.00
flash_ctrl_integrity 346.830s 4786.104us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1229.200s 161077.717us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.210s 757.814us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 9.510s 22.588us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 9.250s 21.785us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1733.650s 3761.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.920s 363.172us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 288.020s 2813.930us 1 1 100.00