Simulation Results: hmac

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.38 %
  • code
  • 97.55 %
  • assert
  • 97.38 %
  • func
  • 43.21 %
  • line
  • 99.54 %
  • branch
  • 98.51 %
  • cond
  • 95.56 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.900s 80.047us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.810s 27.565us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.690s 18.880us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.150s 466.508us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.260s 518.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.170s 29.007us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.690s 18.880us 1 1 100.00
hmac_csr_aliasing 5.260s 518.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 45.900s 1600.919us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 72.260s 2371.059us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 219.380s 38195.493us 1 1 100.00
hmac_test_sha384_vectors 20.670s 327.556us 1 1 100.00
hmac_test_sha512_vectors 20.790s 349.375us 1 1 100.00
hmac_test_hmac256_vectors 7.680s 495.438us 1 1 100.00
hmac_test_hmac384_vectors 11.900s 1857.033us 1 1 100.00
hmac_test_hmac512_vectors 14.190s 3196.333us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.570s 391.031us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 416.630s 4427.959us 1 1 100.00
error 1 1 100.00
hmac_error 13.770s 1414.857us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 13.890s 1809.790us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.900s 80.047us 1 1 100.00
hmac_long_msg 45.900s 1600.919us 1 1 100.00
hmac_back_pressure 72.260s 2371.059us 1 1 100.00
hmac_datapath_stress 416.630s 4427.959us 1 1 100.00
hmac_burst_wr 15.570s 391.031us 1 1 100.00
hmac_stress_all 0.620s 23.111us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.900s 80.047us 1 1 100.00
hmac_long_msg 45.900s 1600.919us 1 1 100.00
hmac_back_pressure 72.260s 2371.059us 1 1 100.00
hmac_datapath_stress 416.630s 4427.959us 1 1 100.00
hmac_wipe_secret 13.890s 1809.790us 1 1 100.00
hmac_test_sha256_vectors 219.380s 38195.493us 1 1 100.00
hmac_test_sha384_vectors 20.670s 327.556us 1 1 100.00
hmac_test_sha512_vectors 20.790s 349.375us 1 1 100.00
hmac_test_hmac256_vectors 7.680s 495.438us 1 1 100.00
hmac_test_hmac384_vectors 11.900s 1857.033us 1 1 100.00
hmac_test_hmac512_vectors 14.190s 3196.333us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.900s 80.047us 1 1 100.00
hmac_long_msg 45.900s 1600.919us 1 1 100.00
hmac_back_pressure 72.260s 2371.059us 1 1 100.00
hmac_datapath_stress 416.630s 4427.959us 1 1 100.00
hmac_burst_wr 15.570s 391.031us 1 1 100.00
hmac_error 13.770s 1414.857us 1 1 100.00
hmac_wipe_secret 13.890s 1809.790us 1 1 100.00
hmac_test_sha256_vectors 219.380s 38195.493us 1 1 100.00
hmac_test_sha384_vectors 20.670s 327.556us 1 1 100.00
hmac_test_sha512_vectors 20.790s 349.375us 1 1 100.00
hmac_test_hmac256_vectors 7.680s 495.438us 1 1 100.00
hmac_test_hmac384_vectors 11.900s 1857.033us 1 1 100.00
hmac_test_hmac512_vectors 14.190s 3196.333us 1 1 100.00
hmac_stress_all 0.620s 23.111us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 0.620s 23.111us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 167.911us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.810s 15.313us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.180s 84.671us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.180s 84.671us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.810s 27.565us 1 1 100.00
hmac_csr_rw 0.690s 18.880us 1 1 100.00
hmac_csr_aliasing 5.260s 518.497us 1 1 100.00
hmac_same_csr_outstanding 1.200s 78.054us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.810s 27.565us 1 1 100.00
hmac_csr_rw 0.690s 18.880us 1 1 100.00
hmac_csr_aliasing 5.260s 518.497us 1 1 100.00
hmac_same_csr_outstanding 1.200s 78.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.070s 228.053us 1 1 100.00
hmac_tl_intg_err 3.720s 2750.349us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.720s 2750.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.900s 80.047us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 8.320s 1099.816us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 144.700s 5642.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.650s 280.118us 1 1 100.00