Simulation Results

Simulation Results: i2c

15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.29 %

code
81.76 %

assert
97.46 %

func
82.66 %

line
96.75 %

branch
92.69 %

cond
84.89 %

toggle
89.24 %

FSM
45.24 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	42.450s	4703.459us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	4.750s	557.863us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.930s	23.013us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.940s	40.098us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.960s	610.883us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.350s	294.407us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.930s	43.421us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.940s	40.098us	1	1	100.00
	i2c_csr_aliasing	1.350s	294.407us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.950s	76.849us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	0.880s	18.449us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	143.250s	24152.424us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.830s	26.144us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	62.390s	4339.399us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	72.190s	2061.509us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.060s	92.503us	1	1	100.00
	i2c_host_fifo_fmt_empty	9.350s	1370.297us	1	1	100.00
	i2c_host_fifo_reset_rx	2.170s	556.136us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	116.190s	7459.423us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	18.240s	1170.979us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.900s	23.001us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.020s	948.402us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	152.860s	25081.313us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.080s	4245.810us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	6.280s	245.924us	1	1	100.00
	i2c_target_intr_smoke	2.710s	1623.564us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.940s	472.247us	1	1	100.00
	i2c_target_fifo_reset_tx	0.940s	199.699us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	85.310s	37338.375us	1	1	100.00
	i2c_target_stress_rd	6.280s	245.924us	1	1	100.00
	i2c_target_intr_stress_wr	5.170s	10193.371us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.460s	2485.638us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	7.020s	3624.179us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.030s	5565.089us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	4.190s	11225.554us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.820s	532.562us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.620s	813.140us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	143.250s	24152.424us	1	1	100.00
	i2c_host_perf_precise	546.230s	23368.639us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	18.240s	1170.979us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.950s	160.453us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.910s	706.909us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.650s	446.974us	1	1	100.00
	i2c_target_nack_txstretch	1.540s	494.765us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.170s	1185.331us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.700s	426.061us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.650s	20.680us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.800s	58.614us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.470s	31.311us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.470s	31.311us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.930s	23.013us	1	1	100.00
	i2c_csr_rw	0.940s	40.098us	1	1	100.00
	i2c_csr_aliasing	1.350s	294.407us	1	1	100.00
	i2c_same_csr_outstanding	1.390s	31.254us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.930s	23.013us	1	1	100.00
	i2c_csr_rw	0.940s	40.098us	1	1	100.00
	i2c_csr_aliasing	1.350s	294.407us	1	1	100.00
	i2c_same_csr_outstanding	1.390s	31.254us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.610s	85.756us	1	1	100.00
	i2c_sec_cm	0.870s	154.405us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.610s	85.756us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.500s	1227.617us	1
target_error_intr				1
	i2c_target_unexp_stop	0.970s	38.565us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	14.590s	1303.492us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	45296288867338929438901094674151468181694737726186081103655741172172107700135	88	UVM_INFO @ 76848930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	82973332416090400771305706450706790488744170896976859021570157219461051417877	86	UVM_INFO @ 18448903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	104890803397853451992251134079864314290145133756469088617272752296145500178658	105	UVM_INFO @ 1227616962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	104004561958436163570186758740830735184571202640861391907472349944147681179777	89	UVM_INFO @ 1303492073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	6181132351644641145782811838128017961402686236247288965459379675317249954839	84	UVM_INFO @ 948402192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	32455398365190511651548188263512305956711186941533333934617789802574396828556	78	UVM_INFO @ 38564835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	13113049313073428507891254805981490399732635018101170450738005090009507872243	79	UVM_INFO @ 11225554495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	69274456712773617832528887533763308590624033184134022518863103341388322234599	79	UVM_INFO @ 23000798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---