Simulation Results: keymgr

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.79 %
  • code
  • 91.86 %
  • assert
  • 97.49 %
  • func
  • 50.02 %
  • line
  • 98.72 %
  • branch
  • 97.53 %
  • cond
  • 92.88 %
  • toggle
  • 84.10 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.530s 493.915us 1 1 100.00
random 1 1 100.00
keymgr_random 5.010s 575.752us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.670s 65.206us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 12.470s 1621.472us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 8.140s 436.639us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.020s 99.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
keymgr_csr_aliasing 8.140s 436.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.710s 1439.814us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.590s 224.822us 1 1 100.00
keymgr_sideload_kmac 3.030s 427.297us 1 1 100.00
keymgr_sideload_aes 3.940s 384.220us 1 1 100.00
keymgr_sideload_otbn 3.700s 107.202us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 6.650s 631.390us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.250s 170.529us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.960s 540.078us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.000s 440.372us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.830s 52.354us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.040s 107.539us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 2.170s 292.782us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.830s 29.001us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.990s 16.081us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 3.290s 241.287us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 3.290s 241.287us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.670s 65.206us 1 1 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
keymgr_csr_aliasing 8.140s 436.639us 1 1 100.00
keymgr_same_csr_outstanding 1.900s 671.112us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.670s 65.206us 1 1 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
keymgr_csr_aliasing 8.140s 436.639us 1 1 100.00
keymgr_same_csr_outstanding 1.900s 671.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
keymgr_tl_intg_err 5.110s 645.868us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.950s 124.269us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.950s 124.269us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.950s 124.269us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.950s 124.269us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.040s 116.040us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.110s 645.868us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.950s 124.269us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.710s 1439.814us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 5.010s 575.752us 1 1 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 5.010s 575.752us 1 1 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 5.010s 575.752us 1 1 100.00
keymgr_csr_rw 0.920s 16.564us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.250s 170.529us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.830s 52.354us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.830s 52.354us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 5.010s 575.752us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.090s 94.079us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.350s 245.050us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.250s 170.529us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.350s 245.050us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.350s 245.050us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.350s 245.050us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.860s 1638.236us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.350s 245.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 14.410s 7781.947us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 106747144563822591364825707844193446259260871426254764020099450506113538327938 1584
UVM_INFO @ 7781946882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---