Simulation Results: kmac/masked

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.28 %
  • code
  • 68.14 %
  • assert
  • 96.62 %
  • func
  • 76.07 %
  • line
  • 95.40 %
  • branch
  • 89.60 %
  • cond
  • 82.88 %
  • toggle
  • 29.17 %
  • FSM
  • 43.67 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 66.100s 17177.353us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.020s 39.449us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.020s 47.630us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.270s 807.601us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.020s 502.188us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.820s 41.673us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.020s 47.630us 1 1 100.00
kmac_csr_aliasing 7.020s 502.188us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.870s 15.303us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.040s 141.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 342.780s 6229.315us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 1068.840s 175582.416us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 38.930s 11382.661us 1 1 100.00
kmac_test_vectors_sha3_256 2316.860s 356065.177us 1 1 100.00
kmac_test_vectors_sha3_384 19.690s 1954.887us 1 1 100.00
kmac_test_vectors_sha3_512 846.090s 14150.619us 1 1 100.00
kmac_test_vectors_shake_128 155.840s 10494.451us 1 1 100.00
kmac_test_vectors_shake_256 115.500s 17110.306us 1 1 100.00
kmac_test_vectors_kmac 2.430s 115.393us 1 1 100.00
kmac_test_vectors_kmac_xof 2.160s 113.598us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 3.410s 252.138us 1 1 100.00
app 0 1 0.00
kmac_app 0.990s 91.206us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.320s 67.151us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 1.430s 376.500us 0 1 0.00
error 0 1 0.00
kmac_error 88.840s 18764.120us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.120s 111.491us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.630s 38.672us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 9.790s 1247.535us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.920s 41.328us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.840s 7.243us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.210s 105.239us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 9.580s 1563.036us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.770s 64.075us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.860s 45.017us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.730s 54.995us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.730s 54.995us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.020s 39.449us 1 1 100.00
kmac_csr_rw 1.020s 47.630us 1 1 100.00
kmac_csr_aliasing 7.020s 502.188us 1 1 100.00
kmac_same_csr_outstanding 1.210s 25.451us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.020s 39.449us 1 1 100.00
kmac_csr_rw 1.020s 47.630us 1 1 100.00
kmac_csr_aliasing 7.020s 502.188us 1 1 100.00
kmac_same_csr_outstanding 1.210s 25.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.760s 45.908us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.760s 45.908us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.760s 45.908us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.760s 45.908us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.260s 233.125us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 68.870s 56201.001us 1 1 100.00
kmac_tl_intg_err 3.950s 222.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.950s 222.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.210s 105.239us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 66.100s 17177.353us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 3.410s 252.138us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.760s 45.908us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 68.870s 56201.001us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 68.870s 56201.001us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 68.870s 56201.001us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 66.100s 17177.353us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.210s 105.239us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 68.870s 56201.001us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 1.120s 11.225us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 66.100s 17177.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 16.130s 8974.981us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_sideload_invalid 6768517359595098333943937552243807715986428643065146255408479753268013795898 79
UVM_INFO @ 38672010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 17789237402673484735654146022378507754462824722053782836990507930087053673416 77
UVM_INFO @ 91205705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 115148964765363922897848745745133620740574630760692077305826220204553107456368 77
UVM_INFO @ 67150950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 10231818899260358790597112286801898741427893472094496771736221446005621763972 77
UVM_INFO @ 376500204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 48860584397254879288902310663907316387922076727810789864645367159843772201785 121
UVM_INFO @ 18764120335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 32949269950163549950964367617869935160389680779129986518871506998258473470194 88
UVM_INFO @ 1563036102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 38058694477041057587604194314822087830559357643781459967853983388971245493231 77
UVM_INFO @ 11224782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 32388981067303944003094433507817452239026551217107066866367497616040512615600 136
UVM_INFO @ 8974981420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_key_error 94598606904457462371754171706903365735258282451698760641477259586730322638328 78
UVM_ERROR @ 111491331 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 111491331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 106031793454338976475577013337756562804374179420128016296206749674629254433419 78
UVM_ERROR @ 7243086 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 7243086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---