Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.14 %
  • code
  • 84.11 %
  • assert
  • 94.83 %
  • func
  • 94.48 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.43 %
  • toggle
  • 85.49 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.850s 47.160us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.410s 32.093us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.780s 16.253us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.620s 35.097us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.750s 89.543us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.390s 57.193us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.780s 16.253us 1 1 100.00
lc_ctrl_csr_aliasing 1.750s 89.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 96.534us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.250s 388.767us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.150s 13.013us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.230s 81.900us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.630s 367.183us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_prog_failure 2.230s 81.900us 1 1 100.00
lc_ctrl_errors 5.630s 367.183us 1 1 100.00
lc_ctrl_security_escalation 5.120s 3282.790us 1 1 100.00
lc_ctrl_jtag_state_failure 21.400s 1089.224us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.610s 330.366us 1 1 100.00
lc_ctrl_jtag_errors 19.810s 3656.450us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.910s 57.745us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.480s 2317.351us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.610s 330.366us 1 1 100.00
lc_ctrl_jtag_errors 19.810s 3656.450us 1 1 100.00
lc_ctrl_jtag_access 6.140s 1244.045us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.430s 775.435us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.810s 1078.086us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.730s 487.168us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.080s 6831.568us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.190s 1637.595us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.870s 168.792us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.550s 100.899us 1 1 100.00
lc_ctrl_jtag_alert_test 1.220s 71.902us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.890s 1084.204us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.100s 24.293us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 30.580s 5750.800us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.200s 16.174us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.680s 460.772us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.680s 460.772us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.410s 32.093us 1 1 100.00
lc_ctrl_csr_rw 0.780s 16.253us 1 1 100.00
lc_ctrl_csr_aliasing 1.750s 89.543us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.060s 53.775us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.410s 32.093us 1 1 100.00
lc_ctrl_csr_rw 0.780s 16.253us 1 1 100.00
lc_ctrl_csr_aliasing 1.750s 89.543us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.060s 53.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
lc_ctrl_tl_intg_err 1.940s 498.205us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.940s 498.205us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.250s 388.767us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.970s 302.472us 1 1 100.00
lc_ctrl_sec_cm 6.810s 541.268us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.120s 3282.790us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 96.534us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.480s 2317.351us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.580s 468.022us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.580s 468.022us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.490s 1184.365us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.080s 336.489us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.080s 336.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 47.040s 4228.711us 1 1 100.00