Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.54 %
  • code
  • 82.15 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.13 %
  • branch
  • 93.23 %
  • cond
  • 79.20 %
  • toggle
  • 80.46 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.610s 27.341us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.080s 62.307us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 19.019us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.380s 109.996us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 52.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.210s 48.017us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 19.019us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 52.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.830s 204.993us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.760s 1798.542us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 73.813us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.940s 208.450us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.640s 1724.590us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_prog_failure 1.940s 208.450us 1 1 100.00
lc_ctrl_errors 8.640s 1724.590us 1 1 100.00
lc_ctrl_security_escalation 5.620s 422.345us 1 1 100.00
lc_ctrl_jtag_state_failure 15.630s 1261.389us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.870s 107.256us 1 1 100.00
lc_ctrl_jtag_errors 22.400s 1067.820us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.730s 1679.861us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.260s 2910.401us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.870s 107.256us 1 1 100.00
lc_ctrl_jtag_errors 22.400s 1067.820us 1 1 100.00
lc_ctrl_jtag_access 3.020s 631.221us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.880s 3742.962us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.130s 79.273us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.260s 55.740us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.800s 1283.688us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.700s 1333.302us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.550s 279.442us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.900s 351.018us 1 1 100.00
lc_ctrl_jtag_alert_test 3.040s 130.847us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.990s 455.578us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.290s 63.213us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 41.900s 3791.228us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.330s 20.711us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.050s 684.492us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.050s 684.492us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.080s 62.307us 1 1 100.00
lc_ctrl_csr_rw 0.850s 19.019us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 52.123us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 18.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.080s 62.307us 1 1 100.00
lc_ctrl_csr_rw 0.850s 19.019us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 52.123us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 18.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
lc_ctrl_tl_intg_err 4.170s 228.527us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 4.170s 228.527us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.760s 1798.542us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.540s 364.152us 1 1 100.00
lc_ctrl_sec_cm 6.280s 757.293us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.620s 422.345us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.830s 204.993us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.260s 2910.401us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.810s 1452.508us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.810s 1452.508us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.350s 1590.594us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.680s 1813.415us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.680s 1813.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.255s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
lc_ctrl_stress_all_with_rand_reset 51198394808939945829904433194493938267384973579409808521018942351432069945632 None