Simulation Results: otbn

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.36 %
  • code
  • 95.50 %
  • assert
  • 90.56 %
  • func
  • 97.03 %
  • block
  • 99.43 %
  • line
  • 99.56 %
  • branch
  • 92.95 %
  • toggle
  • 91.92 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 379.131us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 31.000s 35.222us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 30.000s 41.779us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 34.000s 85.957us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 30.000s 26.188us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 32.000s 70.108us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 30.000s 41.779us 1 1 100.00
otbn_csr_aliasing 30.000s 26.188us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 65.000s 6177.588us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 20.000s 348.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 18.000s 134.108us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 45.000s 705.884us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 30.000s 302.182us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 21.000s 287.993us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 28.000s 724.380us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.732us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 26.288us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 31.000s 46.644us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 19.000s 13.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 271.024us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 271.024us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 31.000s 35.222us 1 1 100.00
otbn_csr_rw 30.000s 41.779us 1 1 100.00
otbn_csr_aliasing 30.000s 26.188us 1 1 100.00
otbn_same_csr_outstanding 4.000s 29.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 31.000s 35.222us 1 1 100.00
otbn_csr_rw 30.000s 41.779us 1 1 100.00
otbn_csr_aliasing 30.000s 26.188us 1 1 100.00
otbn_same_csr_outstanding 4.000s 29.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 32.000s 48.901us 1 1 100.00
otbn_dmem_err 35.000s 95.070us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 51.000s 82.603us 1 1 100.00
otbn_controller_ispr_rdata_err 34.000s 231.472us 1 1 100.00
otbn_mac_bignum_acc_err 16.000s 829.171us 1 1 100.00
otbn_urnd_err 4.000s 10.417us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 28.000s 51.883us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 11.000s 35.750us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 33.047us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
otbn_tl_intg_err 11.000s 131.784us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 22.000s 96.610us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 379.131us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 35.000s 95.070us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 32.000s 48.901us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 11.000s 131.784us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 724.380us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 32.000s 48.901us 1 1 100.00
otbn_dmem_err 35.000s 95.070us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.732us 1 1 100.00
otbn_illegal_mem_acc 28.000s 51.883us 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 32.000s 48.901us 1 1 100.00
otbn_dmem_err 35.000s 95.070us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.732us 1 1 100.00
otbn_illegal_mem_acc 28.000s 51.883us 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 724.380us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 32.000s 48.901us 1 1 100.00
otbn_dmem_err 35.000s 95.070us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.732us 1 1 100.00
otbn_illegal_mem_acc 28.000s 51.883us 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_ctrl_redun 0 1 0.00
otbn_ctrl_redun 30.000s 34.595us 0 1 0.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 191.035us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 23.000s 207.177us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 23.000s 207.177us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 43.752us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 117.564us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 93.287us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 93.287us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 14.000s 35.492us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 30.000s 302.182us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 14.000s 35.466us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 116.517us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 120.000s 713.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 324.000s 14877.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 122.414us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_ctrl_redun 115476147694454389305046826977241395842509549385030093416205607930400745141790 109
UVM_ERROR @ 34594923 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 34594923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---