Simulation Results: pattgen

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.48 %
  • code
  • 98.71 %
  • assert
  • 98.78 %
  • func
  • 88.94 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.13 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 40.571us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 45.754us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 45.258us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 757.413us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 72.828us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 56.811us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 45.258us 1 1 100.00
pattgen_csr_aliasing 1.000s 72.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 23.000s 2737.549us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 18.000s 2619.770us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 38.657us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 7037.000s 1343649.819us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 18.146us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 14.303us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 50.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 50.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 45.754us 1 1 100.00
pattgen_csr_rw 1.000s 45.258us 1 1 100.00
pattgen_csr_aliasing 1.000s 72.828us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 347.414us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 45.754us 1 1 100.00
pattgen_csr_rw 1.000s 45.258us 1 1 100.00
pattgen_csr_aliasing 1.000s 72.828us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 347.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 259.144us 1 1 100.00
pattgen_sec_cm 2.000s 943.698us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 259.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 46.000s 5593.760us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 59.997us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 64857769951049400824325545337766001935268146479624108364939763635264668866013 121
UVM_ERROR @ 1262916028 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1262916028 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1263116028 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: 1 test run
pattgen_stress_all 70219329338493959388186155533819529164317606300714803297830496901237407547110 151
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Name Type Size Value
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exp_item pattgen_item - @11153