Simulation Results: pwrmgr

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.93 %
  • code
  • 97.18 %
  • assert
  • 98.43 %
  • func
  • 98.19 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.19 %
  • toggle
  • 99.44 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 27.527us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.850s 51.409us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.650s 76.453us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.260s 771.686us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.160s 37.440us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.860s 52.951us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.650s 76.453us 1 1 100.00
pwrmgr_csr_aliasing 1.160s 37.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.940s 276.682us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.940s 276.682us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.840s 154.687us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 140.872us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.860s 52.464us 1 1 100.00
pwrmgr_reset_invalid 0.870s 105.202us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.860s 52.464us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.720s 111.911us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.810s 42.996us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.790s 208.316us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 5.180s 11372.825us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.690s 45.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.170s 34.798us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.170s 34.798us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.850s 51.409us 1 1 100.00
pwrmgr_csr_rw 0.650s 76.453us 1 1 100.00
pwrmgr_csr_aliasing 1.160s 37.440us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 70.726us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.850s 51.409us 1 1 100.00
pwrmgr_csr_rw 0.650s 76.453us 1 1 100.00
pwrmgr_csr_aliasing 1.160s 37.440us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 70.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.220s 194.863us 1 1 100.00
pwrmgr_sec_cm 1.010s 472.086us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.010s 472.086us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.010s 472.086us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.220s 194.863us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.630s 1280.248us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.720s 111.911us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.690s 2055.190us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.840s 91.545us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.730s 51.270us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.010s 472.086us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.010s 472.086us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.010s 472.086us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.810s 69.931us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.810s 35.556us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.710s 234.450us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 76.453us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 76.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.930s 343.742us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 10.240s 30086.244us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 68002757297752760788162837636284977760636019814622225908363384035220738168440 79
UVM_ERROR @ 343742034 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 343742034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 107544233511859011468854835353310822293870200502131777447375089700420149808367 805
UVM_INFO @ 11372825459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---