Simulation Results: rom_ctrl/32kb

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.86 %
  • code
  • 93.93 %
  • assert
  • 96.52 %
  • func
  • 97.14 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 96.29 %
  • toggle
  • 94.76 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.370s 312.815us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.730s 302.150us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.160s 123.793us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.340s 170.309us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 532.664us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.470s 140.296us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.160s 123.793us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 532.664us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.400s 247.958us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.010s 385.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.970s 365.210us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.930s 594.555us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.180s 1079.846us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.740s 258.073us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.900s 293.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.900s 293.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.730s 302.150us 1 1 100.00
rom_ctrl_csr_rw 5.160s 123.793us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 532.664us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.660s 297.906us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.730s 302.150us 1 1 100.00
rom_ctrl_csr_rw 5.160s 123.793us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 532.664us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.660s 297.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.220s 1613.279us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 105.120s 494.595us 1 1 100.00
rom_ctrl_tl_intg_err 24.530s 1231.817us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 105.120s 494.595us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 105.120s 494.595us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.120s 494.595us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 105.120s 494.595us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.370s 312.815us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.370s 312.815us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.370s 312.815us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.530s 1231.817us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
rom_ctrl_kmac_err_chk 7.180s 1079.846us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 31.830s 7420.794us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.220s 1613.279us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.120s 494.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 82.720s 8219.093us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 33114255989695055302599318865908794876628740131443948369243351551078155415089 79
UVM_INFO @ 365209748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 21158549803554657980834405212820777905543450795395792474982920993166127704122 94
UVM_INFO @ 7420794216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---