Simulation Results: rom_ctrl/64kb

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.24 %
  • code
  • 97.19 %
  • assert
  • 97.39 %
  • func
  • 97.14 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 98.51 %
  • toggle
  • 95.52 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.390s 729.779us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.120s 215.719us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.860s 1411.109us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.870s 726.380us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.970s 289.362us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.710s 3059.540us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.860s 1411.109us 1 1 100.00
rom_ctrl_csr_aliasing 6.970s 289.362us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.170s 205.814us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.130s 699.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 8.410s 1034.423us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.250s 3115.027us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.850s 1079.810us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.820s 1066.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.240s 699.116us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.240s 699.116us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.120s 215.719us 1 1 100.00
rom_ctrl_csr_rw 6.860s 1411.109us 1 1 100.00
rom_ctrl_csr_aliasing 6.970s 289.362us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.640s 306.488us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.120s 215.719us 1 1 100.00
rom_ctrl_csr_rw 6.860s 1411.109us 1 1 100.00
rom_ctrl_csr_aliasing 6.970s 289.362us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.640s 306.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.560s 1054.571us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 456.010s 551.058us 1 1 100.00
rom_ctrl_tl_intg_err 99.280s 1591.937us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 456.010s 551.058us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 456.010s 551.058us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 456.010s 551.058us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 456.010s 551.058us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.390s 729.779us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.390s 729.779us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.390s 729.779us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 99.280s 1591.937us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
rom_ctrl_kmac_err_chk 14.850s 1079.810us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.270s 2571.208us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.560s 1054.571us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 456.010s 551.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 308.280s 5429.871us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 62435374191454645751268097750418874221656063671545576829682099891027856988143 79
UVM_INFO @ 1034423326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---