Simulation Results: rstmgr

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.62 %
  • code
  • 99.31 %
  • assert
  • 98.80 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.580s 300.080us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.970s 109.984us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.780s 70.651us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.900s 1260.115us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.060s 441.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.280s 114.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.780s 70.651us 1 1 100.00
rstmgr_csr_aliasing 2.060s 441.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.960s 110.956us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.500s 172.831us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.940s 128.899us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.440s 1522.162us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.440s 1522.162us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.440s 1522.162us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.440s 1522.162us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.190s 7836.959us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.860s 79.610us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.110s 345.191us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.110s 345.191us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.970s 109.984us 1 1 100.00
rstmgr_csr_rw 0.780s 70.651us 1 1 100.00
rstmgr_csr_aliasing 2.060s 441.702us 1 1 100.00
rstmgr_same_csr_outstanding 1.020s 82.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.970s 109.984us 1 1 100.00
rstmgr_csr_rw 0.780s 70.651us 1 1 100.00
rstmgr_csr_aliasing 2.060s 441.702us 1 1 100.00
rstmgr_same_csr_outstanding 1.020s 82.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.800s 16913.341us 1 1 100.00
rstmgr_tl_intg_err 2.490s 937.866us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.800s 16913.341us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.800s 16913.341us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.490s 937.866us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.010s 193.245us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.520s 2804.965us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.130s 301.483us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.800s 16913.341us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 70.651us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 70.651us 1 1 100.00