Simulation Results: rv_timer

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.760s 302.389us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.670s 41.551us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.850s 58.444us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.060s 683.416us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.790s 39.443us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.810s 109.265us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.850s 58.444us 1 1 100.00
rv_timer_csr_aliasing 0.790s 39.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 15.100s 1138.897us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.240s 3227.075us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 452.520s 533714.843us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 452.520s 533714.843us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.340s 6327.726us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.560s 13.301us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 202.182us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.850s 2523.572us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.850s 2523.572us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 41.551us 1 1 100.00
rv_timer_csr_rw 0.850s 58.444us 1 1 100.00
rv_timer_csr_aliasing 0.790s 39.443us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 128.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 41.551us 1 1 100.00
rv_timer_csr_rw 0.850s 58.444us 1 1 100.00
rv_timer_csr_aliasing 0.790s 39.443us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 128.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.710s 149.097us 1 1 100.00
rv_timer_tl_intg_err 0.980s 523.579us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.980s 523.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.690s 1617.174us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.740s 845.774us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 27.890s 9633.949us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 7626525724253716337836603645605055310133358003631147909127694761165626341779 75
UVM_INFO @ 1617174289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 92853085526259756320247782005626569616797763110372293692930825487506635197924 75
UVM_INFO @ 1138896501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 45615509119303649583080971237535413978160149370373576744738367163667770013180 75
UVM_INFO @ 845773516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---