Simulation Results: spi_host

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.85 %
  • code
  • 95.03 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 32.000s 4440.035us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 27.290us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 17.389us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 290.906us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 33.325us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 43.443us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 17.389us 1 1 100.00
spi_host_csr_aliasing 1.000s 33.325us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 36.223us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 18.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 47.626us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 166.806us 1 1 100.00
spi_host_error_cmd 1.000s 17.828us 1 1 100.00
spi_host_event 10.000s 473.344us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 470.677us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 470.677us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 470.677us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 907.000s 177175.833us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 204.114us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 64.316us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 470.677us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 470.677us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 32.000s 4440.035us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 32.000s 4440.035us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 80.614us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 377.941us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 20.000s 6842.265us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 198.768us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 166.806us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 48.891us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 20.574us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 137.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 137.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 27.290us 1 1 100.00
spi_host_csr_rw 1.000s 17.389us 1 1 100.00
spi_host_csr_aliasing 1.000s 33.325us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 32.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 27.290us 1 1 100.00
spi_host_csr_rw 1.000s 17.389us 1 1 100.00
spi_host_csr_aliasing 1.000s 33.325us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 32.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 184.879us 1 1 100.00
spi_host_sec_cm 1.000s 44.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 184.879us 1 1 100.00