Simulation Results: sram_ctrl/main

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 95.99 %
  • assert
  • 97.69 %
  • func
  • 93.20 %
  • block
  • 95.03 %
  • line
  • 95.65 %
  • branch
  • 92.23 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 1425.856us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.580us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.211us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 113.545us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.481us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 2620.373us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 52.211us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.481us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 222.000s 82974.120us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 35.000s 1928.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 22.000s 11280.521us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 126.000s 19606.307us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 117.000s 71125.382us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 35954.457us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 30.000s 9584.882us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 3085.679us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 696.616us 1 1 100.00
sram_ctrl_partial_access_b2b 217.000s 35515.306us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 5.000s 682.854us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 2445.657us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 1581.554us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 2249.159us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 754.888us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 333.000s 45666.976us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 13.972us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 1165.244us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 1165.244us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.580us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.211us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.481us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 74.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.580us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.211us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.481us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 74.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 30577.680us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 915.758us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 1975.348us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 915.758us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 1975.348us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 2249.159us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 2249.159us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.211us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 3085.679us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 3085.679us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 3085.679us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 30.000s 9584.882us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1357.251us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 30577.680us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 720.687us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1425.856us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1425.856us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 3085.679us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 915.758us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 30.000s 9584.882us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 915.758us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 915.758us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 1425.856us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 915.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 17.000s 3542.065us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 108293620952750628348214476260846967021353177320404413214845918701693518256396 86
UVM_INFO @ 682854321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 19610964601534251023569932369261669024750991230110148789947156394306740823715 86
UVM_INFO @ 2445657331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 26753645567107060718837887387425552439873919114459521791261523710532343153150 86
UVM_INFO @ 1581554277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---