Simulation Results: sram_ctrl/ret

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.51 %
  • code
  • 83.27 %
  • assert
  • 97.26 %
  • func
  • 94.00 %
  • block
  • 93.83 %
  • line
  • 94.99 %
  • branch
  • 89.51 %
  • toggle
  • 81.92 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 22.068us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 27.663us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.468us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 240.735us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 28.784us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 86.667us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 20.468us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 28.784us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 762.710us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 781.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 146.262us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 168.000s 14914.725us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 438.550us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 3.000s 89.420us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 6411.976us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 4610.792us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 70.605us 1 1 100.00
sram_ctrl_partial_access_b2b 295.000s 26415.522us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 27.509us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 45.223us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 174.987us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1076.708us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 82.934us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 20.000s 2432.199us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 17.690us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 504.421us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 504.421us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.663us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.468us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 28.784us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.107us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.663us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.468us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 28.784us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1790.881us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1754.412us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 526.807us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1754.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 526.807us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1076.708us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1076.708us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.468us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 4610.792us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 4610.792us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 4610.792us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 6411.976us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 107.991us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1790.881us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 115.987us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 22.068us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 22.068us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 4610.792us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1754.412us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 6411.976us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1754.412us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1754.412us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 22.068us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1754.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 4371.015us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 68391782762614793228357619528348485098583177345381547058044083966480745947608 86
UVM_INFO @ 27508836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 31904515564702285642928787954970453107986375336323210871983441145995815038240 86
UVM_INFO @ 45223148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 56226809351512496128545836338557516033504907177714783643007401491488288953485 86
UVM_INFO @ 174986972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---