Simulation Results: sysrst_ctrl

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.38 %
  • code
  • 89.00 %
  • assert
  • 87.84 %
  • func
  • 58.30 %
  • line
  • 95.03 %
  • branch
  • 96.07 %
  • cond
  • 92.37 %
  • toggle
  • 100.00 %
  • FSM
  • 61.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.390s 2111.862us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.900s 2471.708us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.340s 2431.916us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.590s 2524.820us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.060s 6087.841us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.210s 2048.434us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 58.460s 30851.052us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.970s 2798.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.520s 2721.360us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.210s 2048.434us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.970s 2798.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 21.280s 107150.197us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 34.440s 21578.443us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 5.740s 3514.288us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.160s 2638.486us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.250s 2530.166us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.530s 2146.810us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.860s 4690.084us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.810s 2635.814us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.100s 6053.231us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 22.860s 29881.547us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 6.860s 14982.937us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.730s 2040.441us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.070s 2030.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.090s 2154.898us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.090s 2154.898us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.060s 6087.841us 1 1 100.00
sysrst_ctrl_csr_rw 2.210s 2048.434us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.970s 2798.712us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.440s 10153.721us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.060s 6087.841us 1 1 100.00
sysrst_ctrl_csr_rw 2.210s 2048.434us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.970s 2798.712us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.440s 10153.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 9.060s 22080.923us 1 1 100.00
sysrst_ctrl_tl_intg_err 7.510s 22599.731us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 7.510s 22599.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.660s 5351.350us 1 1 100.00