Simulation Results: uart

 
15/06/2026 15:30:27 DVSim: v1.49.9 sha: 058efa9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.19 %
  • code
  • 95.18 %
  • assert
  • 97.12 %
  • func
  • 54.28 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 94.05 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 5.240s 5542.171us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.700s 16.049us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.770s 30.316us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.430s 140.700us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.910s 128.491us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.800s 57.401us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.770s 30.316us 1 1 100.00
uart_csr_aliasing 0.910s 128.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 3.660s 12685.473us 1 1 100.00
parity 2 2 100.00
uart_smoke 5.240s 5542.171us 1 1 100.00
uart_tx_rx 3.660s 12685.473us 1 1 100.00
parity_error 2 2 100.00
uart_intr 3.900s 14246.923us 1 1 100.00
uart_rx_parity_err 19.260s 77588.320us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 3.660s 12685.473us 1 1 100.00
uart_intr 3.900s 14246.923us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 160.070s 136970.069us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 7.900s 35044.056us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 6.000s 48549.814us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 3.900s 14246.923us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 3.900s 14246.923us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 3.900s 14246.923us 1 1 100.00
perf 1 1 100.00
uart_perf 160.920s 12728.715us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.870s 2329.061us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.870s 2329.061us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 7.150s 7446.628us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.150s 3610.177us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 5.390s 7010.531us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 11.700s 5968.860us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 205.570s 80876.751us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 176.030s 92414.905us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.660s 16.287us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 17.318us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.900s 70.642us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.900s 70.642us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.700s 16.049us 1 1 100.00
uart_csr_rw 0.770s 30.316us 1 1 100.00
uart_csr_aliasing 0.910s 128.491us 1 1 100.00
uart_same_csr_outstanding 0.700s 14.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.700s 16.049us 1 1 100.00
uart_csr_rw 0.770s 30.316us 1 1 100.00
uart_csr_aliasing 0.910s 128.491us 1 1 100.00
uart_same_csr_outstanding 0.700s 14.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.130s 694.253us 1 1 100.00
uart_tl_intg_err 1.420s 100.494us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.420s 100.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 15.090s 1649.175us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 108048834503973731880580827116058133557177736223404384382328818978354735375305 75
UVM_ERROR @ 6578285821 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6578366629 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6578386831 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6578427235 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata