Simulation Results: adc_ctrl

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.87 %
  • code
  • 94.99 %
  • assert
  • 92.54 %
  • func
  • 13.07 %
  • line
  • 98.80 %
  • branch
  • 97.28 %
  • cond
  • 87.22 %
  • toggle
  • 99.76 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 8.970s 5964.896us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.400s 1136.012us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.390s 442.196us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 49.160s 26857.083us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1096.262us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.350s 459.962us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.390s 442.196us 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1096.262us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.720s 346.635us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.770s 381.106us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.790s 466.361us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.860s 401.950us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.840s 429.728us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.760s 309.236us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.910s 347.281us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.790s 346.982us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.450s 2893.748us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 15.840s 22039.233us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 114.280s 139493.822us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 8.660s 11282.843us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.180s 460.595us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.260s 478.839us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.110s 427.773us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.110s 427.773us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.400s 1136.012us 1 1 100.00
adc_ctrl_csr_rw 1.390s 442.196us 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1096.262us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.070s 4664.722us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.400s 1136.012us 1 1 100.00
adc_ctrl_csr_rw 1.390s 442.196us 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1096.262us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.070s 4664.722us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 6.150s 4302.993us 1 1 100.00
adc_ctrl_tl_intg_err 8.100s 8743.894us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.100s 8743.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.240s 1190.937us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 35190157904567212910824113660922668864701584260014070145517188241484227435886 386
UVM_INFO @ 346634959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 72154372313977946470465309947725825946105405251206417352709950374991163398411 386
UVM_INFO @ 381105739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 90166203388190562077281169642468929841152227397949277278357795779344617519815 386
UVM_INFO @ 466360565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 38820280687986846901486024767405875648280407890893135705696036491431487739735 386
UVM_INFO @ 401949793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 93077925158149792965006543296524949373743880306776019568772237414072985135616 386
UVM_INFO @ 429728110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 24336926541628004639662908412828823589670732951893847447078577632455321413103 386
UVM_INFO @ 309236478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 21763005047022109405148020538566196867430527439593892155180316152471858024796 386
UVM_INFO @ 346982445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 111622848317662393066099504550427153861236085450937733625149417498690917509994 386
UVM_INFO @ 347281440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 67737222178789895647411379526201125074157308253141495957036699427905868163771 421
UVM_INFO @ 1190936742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 101511198967723382232419165586863216781125652007363370733520190747677526220207 401
UVM_INFO @ 11282843376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---