Simulation Results: aes/unmasked

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.14 %
  • code
  • 88.75 %
  • assert
  • 97.73 %
  • func
  • 74.95 %
  • block
  • 89.04 %
  • line
  • 91.54 %
  • branch
  • 78.97 %
  • toggle
  • 97.81 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 223.854us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 63.411us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 83.812us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 92.910us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 311.898us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 742.885us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 85.111us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 92.910us 1 1 100.00
aes_csr_aliasing 3.000s 742.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 63.411us 1 1 100.00
aes_config_error 2.000s 734.972us 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 63.411us 1 1 100.00
aes_config_error 2.000s 734.972us 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 197.241us 1 1 100.00
aes_b2b 2.000s 181.821us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 63.411us 1 1 100.00
aes_config_error 2.000s 734.972us 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
aes_alert_reset 2.000s 68.570us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 78.479us 1 1 100.00
aes_config_error 2.000s 734.972us 1 1 100.00
aes_alert_reset 2.000s 68.570us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 85.783us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 916.174us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 68.570us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 197.241us 1 1 100.00
aes_sideload 4.000s 76.985us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 57.634us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 13.000s 1307.183us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 74.348us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 201.416us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 201.416us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.812us 1 1 100.00
aes_csr_rw 2.000s 92.910us 1 1 100.00
aes_csr_aliasing 3.000s 742.885us 1 1 100.00
aes_same_csr_outstanding 3.000s 179.010us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.812us 1 1 100.00
aes_csr_rw 2.000s 92.910us 1 1 100.00
aes_csr_aliasing 3.000s 742.885us 1 1 100.00
aes_same_csr_outstanding 3.000s 179.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 28.720us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 396.829us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 296.776us 1 1 100.00
aes_tl_intg_err 2.000s 348.245us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 348.245us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 68.570us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 63.411us 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
aes_alert_reset 2.000s 68.570us 1 1 100.00
aes_core_fi 3.000s 107.627us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 734.972us 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
aes_core_fi 3.000s 107.627us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 4.000s 401.318us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 52.721us 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 197.241us 1 1 100.00
aes_sideload 4.000s 76.985us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 52.721us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 52.721us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 52.721us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 52.721us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 52.721us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 197.241us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 180.649us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
aes_ctr_fi 2.000s 52.949us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 180.649us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 180.649us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_ctr_fi 2.000s 52.949us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 180.649us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
aes_ctr_fi 2.000s 52.949us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 68.570us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
aes_ctr_fi 2.000s 52.949us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
aes_ctr_fi 2.000s 52.949us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_ctr_fi 2.000s 52.949us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 180.649us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 180.649us 0 1 0.00
aes_control_fi 2.000s 68.665us 1 1 100.00
aes_cipher_fi 22.000s 10010.863us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 2.305us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 111620173411676580111769331234043417596887219522737722491030588024597270912905 5456
UVM_INFO @ 28720371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 17296697337236095809377802281292278311600600965682256476698808886566258288703 6420
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 73430918291430358240662980206712305479592790203092409781839212404574230091142 150
UVM_INFO @ 10010862590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 15182277766605911455383579636509507545330351404469774264732185200653304614644 135
UVM_INFO @ 2305218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---