Simulation Results: alert_handler

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.37 %
  • code
  • 90.30 %
  • assert
  • 98.05 %
  • func
  • 76.75 %
  • line
  • 99.66 %
  • branch
  • 98.90 %
  • cond
  • 92.43 %
  • toggle
  • 87.91 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 41.790s 2364.257us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.840s 1786.166us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.290s 81.656us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 186.150s 5493.941us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 80.020s 8722.321us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.530s 252.810us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.290s 81.656us 1 1 100.00
alert_handler_csr_aliasing 80.020s 8722.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 62.530s 1889.874us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 43.820s 5182.285us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1792.820s 200069.339us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 25.860s 731.272us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 41.790s 2364.257us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 26.410s 906.424us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 31.280s 1164.468us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 167.010s 6861.856us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1132.660s 39012.439us 1 1 100.00
alert_handler_lpg_stub_clk 1835.350s 108616.211us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2731.120s 154498.696us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.550s 422.214us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.070s 36.212us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.210s 34.937us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 11.510s 212.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 11.510s 212.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.840s 1786.166us 1 1 100.00
alert_handler_csr_rw 2.290s 81.656us 1 1 100.00
alert_handler_csr_aliasing 80.020s 8722.321us 1 1 100.00
alert_handler_same_csr_outstanding 31.590s 2552.378us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.840s 1786.166us 1 1 100.00
alert_handler_csr_rw 2.290s 81.656us 1 1 100.00
alert_handler_csr_aliasing 80.020s 8722.321us 1 1 100.00
alert_handler_same_csr_outstanding 31.590s 2552.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 95.330s 2951.988us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 95.330s 2951.988us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 95.330s 2951.988us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 95.330s 2951.988us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 344.930s 17773.542us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
alert_handler_tl_intg_err 3.410s 72.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.410s 72.002us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 95.330s 2951.988us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 41.790s 2364.257us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 41.790s 2364.257us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 41.790s 2364.257us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 41.790s 2364.257us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 25.860s 731.272us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1132.660s 39012.439us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 25.860s 731.272us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1792.820s 200069.339us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1792.820s 200069.339us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 16.340s 3469.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 57.960s 1424.273us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 18479679514088442414469153664413006474475474934869559388881232230910496733280 117
UVM_INFO @ 6861856490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 23119573122662989860711160779744404162744724339770579352816436103184583520862 202
UVM_INFO @ 422213503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 43401257707833639754614665798377105827121233612335528267280136141408919138397 118
UVM_INFO @ 1424273270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---